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Legic: adjusted sampling to new ssp clock speed

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Sampling is 4 times faster and pipeline daly reduced to 1/4.
The new code samples each bit earyler to account for the
shorter pipeline. That introduced bit errors by leeking the
next bit into the current one.
This commit is contained in:
Andreas Dröscher 2018-08-19 22:57:38 +02:00
commit 043b0ced06
1 changed files with 3 additions and 1 deletions
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4
armsrc/legicrf.c
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@ -141,7 +141,7 @@ static inline int32_t sample_power() {
static inline bool rx_bit_as_reader() { static inline bool rx_bit_as_reader() {
int32_t power; int32_t power;
for(size_t i = 0; i<5; ++i) { for(size_t i = 0; i<3; ++i) {
power = sample_power(); power = sample_power();
} }
@ -216,6 +216,7 @@ static uint32_t rx_frame_as_reader(uint8_t len) {
// rx_bit_as_reader runs only 95us, resync to TAG_BIT_PERIOD // rx_bit_as_reader runs only 95us, resync to TAG_BIT_PERIOD
last_frame_end += TAG_BIT_PERIOD; last_frame_end += TAG_BIT_PERIOD;
while(GET_TICKS < last_frame_end) { };
} }
return frame; return frame;
@ -239,6 +240,7 @@ static bool rx_ack_as_reader() {
// rx_bit_as_reader runs only 95us, resync to TAG_BIT_PERIOD // rx_bit_as_reader runs only 95us, resync to TAG_BIT_PERIOD
last_frame_end += TAG_BIT_PERIOD; last_frame_end += TAG_BIT_PERIOD;
while(GET_TICKS < last_frame_end) { };
// check if it was an ACK // check if it was an ACK
if(ack) { if(ack) {