From 043b0ced06bf45f972882cbc7eea8eaa23e0c02c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20Dr=C3=B6scher?= Date: Sun, 19 Aug 2018 22:57:38 +0200 Subject: [PATCH] Legic: adjusted sampling to new ssp clock speed Sampling is 4 times faster and pipeline daly reduced to 1/4. The new code samples each bit earyler to account for the shorter pipeline. That introduced bit errors by leeking the next bit into the current one. --- armsrc/legicrf.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/armsrc/legicrf.c b/armsrc/legicrf.c index f1347a39..da469325 100644 --- a/armsrc/legicrf.c +++ b/armsrc/legicrf.c @@ -141,7 +141,7 @@ static inline int32_t sample_power() { static inline bool rx_bit_as_reader() { int32_t power; - for(size_t i = 0; i<5; ++i) { + for(size_t i = 0; i<3; ++i) { power = sample_power(); } @@ -216,6 +216,7 @@ static uint32_t rx_frame_as_reader(uint8_t len) { // rx_bit_as_reader runs only 95us, resync to TAG_BIT_PERIOD last_frame_end += TAG_BIT_PERIOD; + while(GET_TICKS < last_frame_end) { }; } return frame; @@ -239,6 +240,7 @@ static bool rx_ack_as_reader() { // rx_bit_as_reader runs only 95us, resync to TAG_BIT_PERIOD last_frame_end += TAG_BIT_PERIOD; + while(GET_TICKS < last_frame_end) { }; // check if it was an ACK if(ack) {