15 commits

Author	SHA1	Message	Date
n-hutton	990e7b5e1f	add bitfiles for prox ultimate build	2025-06-08 06:26:33 +01:00
n-hutton	3ef1486e79	change seed, making new iclass builds work again	2025-06-04 22:03:56 +01:00
Antiklesys	a04fa57f86	Fpga images from orca release ... Fpga images from orca	2025-06-03 18:09:22 +08:00
n-hutton	0871dfe99a	revert date/time strip because of possible error with blue ice release	2025-06-02 19:25:49 +01:00
n-hutton	982bef6705	fix build failure on linux machines with fwd decl	2025-02-20 15:55:43 +00:00
n-hutton	280b3301ee	PR feedback and make things work generally	2025-02-20 14:51:08 +00:00
iceman1001	b50d921be3	own compiled	2024-02-03 16:11:00 +01:00
Christian Zietz	225bb420c6	Shorten threshold registers to number of used bits	2024-02-03 12:09:02 +01:00
Christian Zietz	dbfd8b7a6d	Make detection threshold for ISO14443A configurable ... This adds a new command "hw sethfthresh" to configure the thresholds used inside the FPGA while demodulating ISO14443A. The thresholds need to be increased on particularly noisy hardware, such as certain Chinese PM3 Easy clones.	2024-02-02 20:51:05 +01:00
iceman1001	e4835e69a3	recompiled the fpga images	2024-01-24 17:06:41 +01:00
iceman1001	85aac72855	new fpga images	2023-08-29 16:46:52 +02:00
iceman1001	ba320f26f7	ensure registers and vars is set correct	2023-08-28 15:34:36 +02:00
iceman1001	114dda1582	After testing and verification its found that the SHALLOW MODULATION in HF is not working well in RDV4. Swapping from PWR_OE4 to PWR_OE1 makes it much better. Thanks to @d18c7db for solution and @gentlekiwi for testing and never giving up on finding the bug	2023-08-28 12:00:44 +02:00
iceman1001	71023d0c6e	regenerated with the HF update	2023-07-12 16:25:14 +02:00
d18c7db	c59bdec4f2	Unified fpga folders	2023-05-30 19:47:27 +02:00