change seed, making new iclass builds work again

2025-07-05 20:41:34 -07:00 · 2025-06-04 22:03:56 +01:00 · 2025-06-04 22:03:56 +01:00 · 3ef1486e79
commit 3ef1486e79
parent 186ed6fb07
6 changed files with 2 additions and 2 deletions
--- a/fpga/Makefile
+++ b/fpga/Makefile
@ -45,7 +45,7 @@ XST_OPTS_AREA += -fsm_style bram
 XST_OPTS_AREA += -fsm_encoding compact

 # par specific option (set determistic seed)
-PAR_OPTIONS = -t 1
+PAR_OPTIONS = -t 2

 # Types of selective module compilation:
 # WITH_LF  Enables selection of LF modules (and disables all HF)
@ -188,7 +188,7 @@ work:
 	$(Q)$(RM) $@ $*.drc $*.rbt
 	$(info [=] BITGEN $@)
 	$(Q)$(XILINX_TOOLS_PREFIX)bitgen $(VERBOSITY) -w $* $@
-	#python3 ../strip_date_time_from_binary.py $@ || true
+	python3 ../strip_date_time_from_binary.py $@ || true
 	$(Q)$(CP) $@ ..

 # Build all targets
--- a/fpga/fpga_icopyx_hf.bit
+++ b/fpga/fpga_icopyx_hf.bit
--- a/fpga/fpga_pm3_felica.bit
+++ b/fpga/fpga_pm3_felica.bit
--- a/fpga/fpga_pm3_hf.bit
+++ b/fpga/fpga_pm3_hf.bit
--- a/fpga/fpga_pm3_hf_15.bit
+++ b/fpga/fpga_pm3_hf_15.bit
--- a/fpga/fpga_pm3_lf.bit
+++ b/fpga/fpga_pm3_lf.bit