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Alex 2023-08-24 18:21:07 +02:00
parent 66b1758278
commit 3e4b7d07ff
10 changed files with 332 additions and 353 deletions
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2
fpga/clk_divider.v
View file

@ -22,7 +22,7 @@ module clk_divider(
);
reg [7:0] div_cnt_ = 0;
reg div_clk_;
reg div_clk_ = 0;
assign div_cnt = div_cnt_;
assign div_clk = div_clk_;

8
fpga/fpga_icopyx_lf.v
View file

@ -71,7 +71,13 @@ reg [7:0] lf_ed_threshold;
wire [7:0] pck_cnt;
wire pck_divclk;
reg [7:0] divisor;
clk_divider div_clk(pck0, divisor, pck_cnt, pck_divclk);
clk_divider div_clk(
.clk (pck0),
.divisor (divisor),
.div_cnt (pck_cnt),
.div_clk (pck_divclk)
);
// We switch modes between transmitting to the 13.56 MHz tag and receiving
// from it, which means that we must make sure that we can do so without

12
fpga/hi_flite.v
View file

@ -75,10 +75,10 @@ reg [8:0] curmax=`imax;
reg after_hysteresis = 1'b1;
//state machine for envelope tracking
reg [1:0] state=1'd0;
reg [1:0] state = 1'd0;
//lower edge detected, trying to detect first bit of SYNC (b24d, 1011001001001101)
reg try_sync=1'b0;
reg try_sync = 1'b0;
//detected first sync bit, phase frozen
reg did_sync=0;
@ -113,7 +113,7 @@ always @(posedge adc_clk)
always @(negedge adc_clk)
begin
//count fc/64 - transfer bits to ARM at the rate they are received
if( ((~speed) && (ssp_cnt[5:0] == 6'b000000)) || (speed && (ssp_cnt[4:0] == 5'b00000)))
if( ((~speed) && (ssp_cnt[5:0] == 6'b000000) ) || (speed && (ssp_cnt[4:0] == 5'b00000)) )
begin
ssp_clk <= 1'b1;
//send current bit (detected in SNIFF mode or the one being modulated in MOD mode, 0 otherwise)
@ -144,7 +144,6 @@ reg[7:0] mid = 8'd128;
// reg sending = 1'b0; // are we actively modulating?
reg [11:0] bit_counts = 12'd0; // for timeslots. only support ts=0 for now, at 212 speed -512 fullbits from end of frame. One hopes. might remove those?
//we need some way to flush bit_counts triggers on mod_type changes don't compile
reg dlay;
always @(negedge adc_clk) // every data ping?
@ -276,7 +275,6 @@ begin
end
end
if (try_sync && tsinceedge < 128)
begin
//detect bits in their middle ssp sampling is in sync, so it would sample all bits in order
@ -309,7 +307,6 @@ begin
mid <= 8'd127;
end
end
end
else
begin
@ -340,9 +337,6 @@ begin
end
end
end
else
begin
end
// sending <= 0;
end

4
fpga/hi_get_trace.v
View file

@ -111,7 +111,6 @@ begin
end
end
// (2+1)k RAM
reg [7:0] D_out1, D_out2;
reg [7:0] ram1 [2047:0]; // 2048 u8
@ -127,7 +126,7 @@ begin
else
D_out1 <= ram1[addr[10:0]];
if (write_enable2)
begin
begin
ram2[addr[9:0]] <= adc_d;
D_out2 <= adc_d;
end
@ -135,7 +134,6 @@ begin
D_out2 <= ram2[addr[9:0]];
end
reg [7:0] shift_out;
always @(negedge ck_1356megb)

15
fpga/hi_iso14443a.v
View file

@ -104,8 +104,6 @@ begin
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Tag -> PM3
// filter the input for a tag's signal. The filter box needs the 4 previous input values and is a gaussian derivative filter
@ -132,7 +130,6 @@ wire [9:0] tmp2 = adc_d_times_2 + input_prev_1;
// convert intermediate signals to signed and calculate the filter output
wire signed [10:0] adc_d_filtered = {1'b0, tmp1} - {1'b0, tmp2};
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// internal FPGA timing. Maximum required period is 128 carrier clock cycles for a full 8 Bit transfer to ARM. (i.e. we need a
// 7 bit counter). Adjust its frequency to external reader's clock when simulating a tag or sniffing.
@ -176,7 +173,6 @@ begin
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Tag -> PM3:
// determine best possible time for starting/resetting the modulation detector.
@ -208,7 +204,6 @@ begin
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Tag -> PM3:
// modulation detector. Looks for the steepest falling and rising edges within a 16 clock period. If there is both a significant
@ -264,7 +259,6 @@ begin
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Tag+Reader -> PM3
// sample 4 bits reader data and 4 bits tag data for sniffing
@ -280,7 +274,6 @@ begin
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// PM3 -> Reader:
// a delay line to ensure that we send the (emulated) tag's answer at the correct time according to ISO14443-3
@ -303,7 +296,6 @@ begin
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// PM3 -> Reader, internal timing:
// a timer for the 1172 cycles fdt (Frame Delay Time). Start the timer with a rising edge of the reader's signal.
@ -366,7 +358,6 @@ begin
if(fdt_counter == `FDT_INDICATOR_COUNT) fdt_indicator <= 1'b1;
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// PM3 -> Reader or Tag
// assign a modulation signal to the antenna. This signal is either a delayed signal (to achieve fdt when sending to a reader)
@ -395,7 +386,6 @@ begin
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// PM3 -> Reader
// determine the required delay in the mod_sig_buf (set mod_sig_ptr).
@ -438,7 +428,6 @@ begin
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// FPGA -> ARM communication:
// buffer 8 bits data to be sent to ARM. Shift them out bit by bit.
@ -482,10 +471,8 @@ begin
to_arm[7:1] <= to_arm[6:0];
end
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// FPGA <-> ARM communication:
// generate a ssp clock and ssp frame signal for the synchronous transfer from/to the ARM
@ -520,7 +507,6 @@ begin
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// FPGA -> ARM communication:
// select the data to be sent to ARM
@ -565,7 +551,6 @@ assign sub_carrier = ~sub_carrier_cnt[3];
// in FPGA_HF_ISO14443A_READER_LISTEN: carrier always on; in other modes: carrier always off
assign pwr_hi = (ck_1356meg & (((mod_type == `FPGA_HF_ISO14443A_READER_MOD) & ~mod_sig_coil) || (mod_type == `FPGA_HF_ISO14443A_READER_LISTEN)));
// Enable HF antenna drivers:
assign pwr_oe1 = 1'b0;
assign pwr_oe3 = 1'b0;

5
fpga/hi_simulate.v
View file

@ -88,7 +88,6 @@ begin
end
end
// Divide 13.56 MHz to produce various frequencies for SSP_CLK
// and modulation.
reg [8:0] ssp_clk_divider;
@ -109,7 +108,6 @@ begin
ssp_clk <= ~ssp_clk_divider[4];
end
// Produce the byte framing signal; the phase of this signal
// is arbitrary, because it's just a bit stream in this module.
always @(negedge adc_clk)
@ -130,7 +128,6 @@ begin
end
end
// Synchronize up the after-hysteresis signal, to produce DIN.
always @(posedge ssp_clk)
ssp_din = after_hysteresis;
@ -149,8 +146,6 @@ always @(*)
else
modulating_carrier <= 1'b0; // yet unused
// Load modulation. Toggle only one of these, since we are already producing much deeper
// modulation than a real tag would.
assign pwr_oe1 = 1'b0; // 33 Ohms Load

68
fpga/lf_edge_detect.v
View file

@ -1,4 +1,3 @@
//-----------------------------------------------------------------------------
// Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
//
@ -30,7 +29,7 @@ module lf_edge_detect(
output edge_toggle
);
min_max_tracker tracker(
min_max_tracker tracker(
.clk (clk),
.adc_d (adc_d),
.threshold (lf_ed_threshold),
@ -38,14 +37,14 @@ module lf_edge_detect(
.max (max)
);
// auto-tune
assign high_threshold = (max + min) / 2 + (max - min) / 4;
assign highz_threshold = (max + min) / 2 + (max - min) / 8;
assign lowz_threshold = (max + min) / 2 - (max - min) / 8;
assign low_threshold = (max + min) / 2 - (max - min) / 4;
// auto-tune
assign high_threshold = (max + min) / 2 + (max - min) / 4;
assign highz_threshold = (max + min) / 2 + (max - min) / 8;
assign lowz_threshold = (max + min) / 2 - (max - min) / 8;
assign low_threshold = (max + min) / 2 - (max - min) / 4;
// heuristic to see if it makes sense to try to detect an edge
wire enabled =
// heuristic to see if it makes sense to try to detect an edge
wire enabled =
(high_threshold > highz_threshold)
& (highz_threshold > lowz_threshold)
& (lowz_threshold > low_threshold)
@ -53,27 +52,27 @@ module lf_edge_detect(
& ((highz_threshold - lowz_threshold) > 16)
& ((lowz_threshold - low_threshold) > 8);
// Toggle the output with hysteresis
// Set to high if the ADC value is above the threshold
// Set to low if the ADC value is below the threshold
reg is_high = 0;
reg is_low = 0;
reg is_zero = 0;
reg trigger_enabled = 1;
reg output_edge = 0;
reg output_state;
// Toggle the output with hysteresis
// Set to high if the ADC value is above the threshold
// Set to low if the ADC value is below the threshold
reg is_high = 0;
reg is_low = 0;
reg is_zero = 0;
reg trigger_enabled = 1;
reg output_edge = 0;
reg output_state;
always @(posedge clk)
begin
always @(posedge clk)
begin
is_high <= (adc_d >= high_threshold);
is_low <= (adc_d <= low_threshold);
is_zero <= ((adc_d > lowz_threshold) & (adc_d < highz_threshold));
end
end
// all edges detection
always @(posedge clk)
if (enabled)
begin
// all edges detection
always @(posedge clk)
if (enabled)
begin
// To enable detecting two consecutive peaks at the same level
// (low or high) we check whether or not we went back near 0 in-between.
// This extra check is necessary to prevent from noise artifacts
@ -82,21 +81,22 @@ module lf_edge_detect(
begin
output_edge <= ~output_edge;
trigger_enabled <= 0;
end else
trigger_enabled <= trigger_enabled | is_zero;
end
else
trigger_enabled <= trigger_enabled | is_zero;
end
// edge states
always @(posedge clk)
if (enabled)
begin
// edge states
always @(posedge clk)
if (enabled)
begin
if (is_high)
output_state <= 1'd1;
else if (is_low)
output_state <= 1'd0;
end
end
assign edge_state = output_state;
assign edge_toggle = output_edge;
assign edge_state = output_state;
assign edge_toggle = output_edge;
endmodule

7
fpga/lo_read.v
View file

@ -51,7 +51,7 @@ reg [7:0] to_arm_shiftreg;
// we read the ADC value when pck_cnt=7 and shift it out on counts 8..15
always @(posedge pck0)
begin
if((pck_cnt == 8'd7) && !pck_divclk)
if ((pck_cnt == 8'd7) && !pck_divclk)
to_arm_shiftreg <= adc_d;
else
begin
@ -73,14 +73,15 @@ end
// _ _ _ _ _ _ _ _ _ _
// ssp_clk |_| |_| |_| |_| |_| |_| |_| |_| |_| |_
// serialized SSP data is gated by ant_lo to suppress unwanted signal
// serialized SSP data is gated by pck_divclk to suppress unwanted signal
assign ssp_din = to_arm_shiftreg[7] && !pck_divclk;
// SSP clock always runs at 24MHz
assign ssp_clk = pck0;
// SSP frame is gated by ant_lo and goes high when pck_divider=8..15
// SSP frame is gated by pck_divclk and goes high when pck_cnt=8..15
assign ssp_frame = (pck_cnt[7:3] == 5'd1) && !pck_divclk;
// unused signals tied low
assign pwr_hi = 1'b0;
// always on outputs, unused
assign pwr_oe1 = 1'b0;
assign pwr_oe2 = 1'b0;
assign pwr_oe3 = 1'b0;

20
fpga/min_max_tracker.v
View file

@ -31,14 +31,14 @@ module min_max_tracker(
output [7:0] max
);
reg [7:0] min_val = 255;
reg [7:0] max_val = 0;
reg [7:0] cur_min_val = 255;
reg [7:0] cur_max_val = 0;
reg [1:0] state = 0;
reg [7:0] min_val = 255;
reg [7:0] max_val = 0;
reg [7:0] cur_min_val = 255;
reg [7:0] cur_max_val = 0;
reg [1:0] state = 0;
always @(posedge clk)
begin
always @(posedge clk)
begin
case (state)
0: // initialize
begin
@ -72,9 +72,9 @@ module min_max_tracker(
end
end
endcase
end
end
assign min = min_val;
assign max = max_val;
assign min = min_val;
assign max = max_val;
endmodule