From 3e4b7d07ff0a4effbc06b114a373bc3b4fa97764 Mon Sep 17 00:00:00 2001 From: Alex Date: Thu, 24 Aug 2023 18:21:07 +0200 Subject: [PATCH] Whitespace, formatting --- fpga/clk_divider.v | 2 +- fpga/fpga_icopyx_lf.v | 8 +- fpga/hi_flite.v | 378 ++++++++++++++++++++--------------------- fpga/hi_get_trace.v | 16 +- fpga/hi_iso14443a.v | 49 ++---- fpga/hi_simulate.v | 19 +-- fpga/lf_edge_detect.v | 120 ++++++------- fpga/lo_edge_detect.v | 4 +- fpga/lo_read.v | 7 +- fpga/min_max_tracker.v | 82 ++++----- 10 files changed, 332 insertions(+), 353 deletions(-) diff --git a/fpga/clk_divider.v b/fpga/clk_divider.v index 0bcc2e608..7cb9925f3 100644 --- a/fpga/clk_divider.v +++ b/fpga/clk_divider.v @@ -22,7 +22,7 @@ module clk_divider( ); reg [7:0] div_cnt_ = 0; - reg div_clk_; + reg div_clk_ = 0; assign div_cnt = div_cnt_; assign div_clk = div_clk_; diff --git a/fpga/fpga_icopyx_lf.v b/fpga/fpga_icopyx_lf.v index b1b890b79..d1495498a 100644 --- a/fpga/fpga_icopyx_lf.v +++ b/fpga/fpga_icopyx_lf.v @@ -71,7 +71,13 @@ reg [7:0] lf_ed_threshold; wire [7:0] pck_cnt; wire pck_divclk; reg [7:0] divisor; -clk_divider div_clk(pck0, divisor, pck_cnt, pck_divclk); + +clk_divider div_clk( + .clk (pck0), + .divisor (divisor), + .div_cnt (pck_cnt), + .div_clk (pck_divclk) +); // We switch modes between transmitting to the 13.56 MHz tag and receiving // from it, which means that we must make sure that we can do so without diff --git a/fpga/hi_flite.v b/fpga/hi_flite.v index ac9e7e069..d93d67d21 100644 --- a/fpga/hi_flite.v +++ b/fpga/hi_flite.v @@ -66,7 +66,7 @@ assign adc_clk = ck_1356meg; `define min_bitdelay_212 8 //minimum values and corresponding thresholds -reg [8:0] curmin=`imin; +reg [8:0] curmin=`imin; reg [8:0] curminthres=`ithrmin; reg [8:0] curmaxthres=`ithrmax; reg [8:0] curmax=`imax; @@ -75,10 +75,10 @@ reg [8:0] curmax=`imax; reg after_hysteresis = 1'b1; //state machine for envelope tracking -reg [1:0] state=1'd0; +reg [1:0] state = 1'd0; //lower edge detected, trying to detect first bit of SYNC (b24d, 1011001001001101) -reg try_sync=1'b0; +reg try_sync = 1'b0; //detected first sync bit, phase frozen reg did_sync=0; @@ -105,32 +105,32 @@ reg zero = 1'b0; // Manchester first halfbit low second high corresponds to this reg [8:0] ssp_cnt = 9'd0; always @(posedge adc_clk) - ssp_cnt <= (ssp_cnt + 1); + ssp_cnt <= (ssp_cnt + 1); //maybe change it so that ARM sends preamble as well. //then: ready bits sent to ARM, 8 bits sent from ARM (all ones), then preamble (all zeros, presumably) - which starts modulation always @(negedge adc_clk) begin - //count fc/64 - transfer bits to ARM at the rate they are received - if( ((~speed) && (ssp_cnt[5:0] == 6'b000000)) || (speed && (ssp_cnt[4:0] == 5'b00000))) - begin - ssp_clk <= 1'b1; - //send current bit (detected in SNIFF mode or the one being modulated in MOD mode, 0 otherwise) - ssp_din <= curbit; - end - if( ( (~speed) && (ssp_cnt[5:0] == 6'b100000)) ||(speed && ssp_cnt[4:0] == 5'b10000)) - ssp_clk <= 1'b0; + //count fc/64 - transfer bits to ARM at the rate they are received + if( ((~speed) && (ssp_cnt[5:0] == 6'b000000) ) || (speed && (ssp_cnt[4:0] == 5'b00000)) ) + begin + ssp_clk <= 1'b1; + //send current bit (detected in SNIFF mode or the one being modulated in MOD mode, 0 otherwise) + ssp_din <= curbit; + end + if( ( (~speed) && (ssp_cnt[5:0] == 6'b100000)) ||(speed && ssp_cnt[4:0] == 5'b10000)) + ssp_clk <= 1'b0; //create frame pulses. TBH, I still don't know what they do exactly, but they are crucial for ARM->FPGA transfer. If the frame is in the beginning of the byte, transfer slows to a crawl for some reason // took me a day to figure THAT out. - if(( (~speed) && (ssp_cnt[8:0] == 9'd31)) || (speed && ssp_cnt[7:0] == 8'd15)) - begin - ssp_frame <= 1'b1; - end - if(( (~speed) && (ssp_cnt[8:0] == 9'b1011111)) || (speed &&ssp_cnt[7:0] == 8'b101111) ) - begin - ssp_frame <= 1'b0; - end + if(( (~speed) && (ssp_cnt[8:0] == 9'd31)) || (speed && ssp_cnt[7:0] == 8'd15)) + begin + ssp_frame <= 1'b1; + end + if(( (~speed) && (ssp_cnt[8:0] == 9'b1011111)) || (speed &&ssp_cnt[7:0] == 8'b101111) ) + begin + ssp_frame <= 1'b0; + end end //previous signal value, mostly to detect SYNC @@ -144,206 +144,200 @@ reg[7:0] mid = 8'd128; // reg sending = 1'b0; // are we actively modulating? reg [11:0] bit_counts = 12'd0; // for timeslots. only support ts=0 for now, at 212 speed -512 fullbits from end of frame. One hopes. might remove those? - //we need some way to flush bit_counts triggers on mod_type changes don't compile reg dlay; always @(negedge adc_clk) // every data ping? begin - //envelope follow code... + //envelope follow code... //////////// - if (fccount == bitmlen) - begin + if (fccount == bitmlen) + begin if ((~try_sync) && (adc_d < curminthres) && disabl ) begin - fccount <= 1; - end - else - begin - fccount <= 0; - end - dlay <= ssp_dout; - if (bit_counts > 768) // should be over ts0 now, without ARM interference... stop counting... - begin - bit_counts <= 0; - end - else - if (power) - bit_counts <= 0; - else - bit_counts <= bit_counts + 1; + fccount <= 1; end else begin + fccount <= 0; + end + dlay <= ssp_dout; + if (bit_counts > 768) // should be over ts0 now, without ARM interference... stop counting... + begin + bit_counts <= 0; + end + else + if (power) + bit_counts <= 0; + else + bit_counts <= bit_counts + 1; + end + else + begin if((~try_sync) && (adc_d < curminthres) && disabl) begin - fccount <= 1; - end - else - begin - fccount <= fccount + 1; - end + fccount <= 1; end + else + begin + fccount <= fccount + 1; + end + end - // rising edge - if (adc_d > curmaxthres) - begin + // rising edge + if (adc_d > curmaxthres) + begin case (state) - 0: begin - curmax <= adc_d > `imax? adc_d : `imax; - state <= 2; + 0: begin + curmax <= adc_d > `imax? adc_d : `imax; + state <= 2; end - 1: begin - curminthres <= ((curmin >> 1) + (curmin >> 2) + (curmin >> 4) + (curmax >> 3) + (curmax >> 4)); //threshold: 0.1875 max + 0.8125 min - curmaxthres <= ((curmax >> 1) + (curmax >> 2) + (curmax >> 4) + (curmin >> 3) + (curmin >> 4)); - curmax <= adc_d > 155 ? adc_d : 155; // to hopefully prevent overflow from spikes going up to 255 - state <= 2; + 1: begin + curminthres <= ((curmin >> 1) + (curmin >> 2) + (curmin >> 4) + (curmax >> 3) + (curmax >> 4)); //threshold: 0.1875 max + 0.8125 min + curmaxthres <= ((curmax >> 1) + (curmax >> 2) + (curmax >> 4) + (curmin >> 3) + (curmin >> 4)); + curmax <= adc_d > 155 ? adc_d : 155; // to hopefully prevent overflow from spikes going up to 255 + state <= 2; end - 2: begin - if (adc_d > curmax) - curmax <= adc_d; - end - default: + 2: begin + if (adc_d > curmax) + curmax <= adc_d; + end + default: begin end endcase after_hysteresis <= 1'b1; if(try_sync) - tsinceedge <= 0; - end - else if (adc_d> 1) + (curmin >> 2) + (curmin >> 4) + (curmax >> 3) + (curmax >> 4)); curmaxthres <= ( (curmax >> 1) + (curmax >> 2) + (curmax >> 4) + (curmin >> 3) + (curmin >> 4)); curmin <= adc_d < `imin ? adc_d : `imin; state <= 1; - end - default: - begin - end - endcase - after_hysteresis <= 0; - if (~try_sync ) //begin modulation, lower edge... - begin - try_sync <= 1; - fccount <= 1; - did_sync <= 0; - curbit <= 0; - mid <= 8'd127; - tsinceedge <= 0; - prv <= 1; - end - else - begin - tsinceedge <= 0; - end - end - else //stable state, low or high - begin - curminthres <= ( (curmin >> 1) + (curmin >> 2) + (curmin >> 4) + (curmax >> 3) + (curmax >> 4)); - curmaxthres <= ( (curmax >> 1) + (curmax >> 2) + (curmax >> 4) + (curmin >> 3) + (curmin >> 4)); - state <= 0; - - if (try_sync ) - begin - if (tsinceedge >= (128)) - begin - //we might need to start counting... assuming ARM wants to reply to the frame. - bit_counts <= 1;// i think? 128 is about 2 bits passed... but 1 also works - try_sync <= 0; - did_sync <= 0;//desync - curmin <= `imin; //reset envelope - curmax <= `imax; - curminthres <= `ithrmin; - curmaxthres <= `ithrmax; - prv <= 1; - tsinceedge <= 0; - after_hysteresis <= 1'b1; - curbit <= 0; - mid <= 8'd128; - end - else - tsinceedge <= (tsinceedge + 1); - end - end - - - if (try_sync && tsinceedge < 128) + end + default: begin - //detect bits in their middle ssp sampling is in sync, so it would sample all bits in order - if (fccount == bithalf) - begin - if ((~did_sync) && ((prv == 1 && (mid > 128))||(prv == 0 && (mid <= 128)))) - begin - //sync the Zero, and set curbit roperly - did_sync <= 1'b1; - zero <= ~prv;// 1-prv - curbit <= 1; - end + end + endcase + after_hysteresis <= 0; + if (~try_sync ) //begin modulation, lower edge... + begin + try_sync <= 1; + fccount <= 1; + did_sync <= 0; + curbit <= 0; + mid <= 8'd127; + tsinceedge <= 0; + prv <= 1; + end + else + begin + tsinceedge <= 0; + end + end + else //stable state, low or high + begin + curminthres <= ( (curmin >> 1) + (curmin >> 2) + (curmin >> 4) + (curmax >> 3) + (curmax >> 4)); + curmaxthres <= ( (curmax >> 1) + (curmax >> 2) + (curmax >> 4) + (curmin >> 3) + (curmin >> 4)); + state <= 0; + + if (try_sync ) + begin + if (tsinceedge >= (128)) + begin + //we might need to start counting... assuming ARM wants to reply to the frame. + bit_counts <= 1;// i think? 128 is about 2 bits passed... but 1 also works + try_sync <= 0; + did_sync <= 0;//desync + curmin <= `imin; //reset envelope + curmax <= `imax; + curminthres <= `ithrmin; + curmaxthres <= `ithrmax; + prv <= 1; + tsinceedge <= 0; + after_hysteresis <= 1'b1; + curbit <= 0; + mid <= 8'd128; + end + else + tsinceedge <= (tsinceedge + 1); + end + end + + if (try_sync && tsinceedge < 128) + begin + //detect bits in their middle ssp sampling is in sync, so it would sample all bits in order + if (fccount == bithalf) + begin + if ((~did_sync) && ((prv == 1 && (mid > 128))||(prv == 0 && (mid <= 128)))) + begin + //sync the Zero, and set curbit roperly + did_sync <= 1'b1; + zero <= ~prv;// 1-prv + curbit <= 1; + end + else + curbit <= (mid > 128) ? (~zero) : zero; + + prv <= (mid > 128) ? 1 : 0; + + if (adc_d > curmaxthres) + mid <= 8'd129; + else if (adc_d < curminthres) + mid <= 8'd127; + else + begin + if (after_hysteresis) + begin + mid <= 8'd129; + end else - curbit <= (mid > 128) ? (~zero) : zero; - - prv <= (mid > 128) ? 1 : 0; - - if (adc_d > curmaxthres) - mid <= 8'd129; - else if (adc_d < curminthres) - mid <= 8'd127; - else - begin - if (after_hysteresis) - begin - mid <= 8'd129; - end - else - begin - mid <= 8'd127; - end - end - - end - else - begin - if (fccount==bitmlen) - begin - // fccount <= 0; - prv <= (mid > 128) ? 1 : 0; - mid <= 128; - end - else - begin + begin + mid <= 8'd127; + end + end + end + else + begin + if (fccount==bitmlen) + begin + // fccount <= 0; + prv <= (mid > 128) ? 1 : 0; + mid <= 128; + end + else + begin // minimum-maximum calc - if(adc_d > curmaxthres) - mid <= mid + 1; - else if (adc_d < curminthres) + if(adc_d > curmaxthres) + mid <= mid + 1; + else if (adc_d < curminthres) mid <= mid - 1; - else + else begin - if (after_hysteresis) - begin - mid <= mid + 1; - end - else - begin - mid <= mid - 1; - end + if (after_hysteresis) + begin + mid <= mid + 1; + end + else + begin + mid <= mid - 1; + end end - end - end end - else - begin - end -// sending <= 0; + end + end +// sending <= 0; end //put modulation here to maintain the correct clock. Seems that some readers are sensitive to that @@ -353,23 +347,23 @@ wire mod = ((fccount >= bithalf) ^ dlay) & (~disabl); always @(ck_1356meg or ssp_dout or power or disabl or mod) begin if (power) - begin + begin pwr_hi <= ck_1356meg; pwr_lo <= 1'b0; pwr_oe1 <= 1'b0;//mod; pwr_oe2 <= 1'b0;//mod; pwr_oe3 <= 1'b0;//mod; pwr_oe4 <= mod;//1'b0; - end + end else - begin + begin pwr_hi <= 1'b0; pwr_lo <= 1'b0; pwr_oe1 <= 1'b0; pwr_oe2 <= 1'b0; pwr_oe3 <= 1'b0; pwr_oe4 <= mod; - end + end end endmodule diff --git a/fpga/hi_get_trace.v b/fpga/hi_get_trace.v index cd33173b2..b577ff6be 100644 --- a/fpga/hi_get_trace.v +++ b/fpga/hi_get_trace.v @@ -105,13 +105,12 @@ begin write_enable1 <= 1'b0; write_enable2 <= 1'b0; if (previous_major_mode != `FPGA_MAJOR_MODE_OFF && previous_major_mode != `FPGA_MAJOR_MODE_HF_GET_TRACE) // just switched off - begin + begin start_addr <= addr; - end + end end end - // (2+1)k RAM reg [7:0] D_out1, D_out2; reg [7:0] ram1 [2047:0]; // 2048 u8 @@ -127,7 +126,7 @@ begin else D_out1 <= ram1[addr[10:0]]; if (write_enable2) -begin + begin ram2[addr[9:0]] <= adc_d; D_out2 <= adc_d; end @@ -135,7 +134,6 @@ begin D_out2 <= ram2[addr[9:0]]; end - reg [7:0] shift_out; always @(negedge ck_1356megb) @@ -150,10 +148,10 @@ begin shift_out <= D_out2; end else - begin - // or shift left - shift_out[7:1] <= shift_out[6:0]; - end + begin + // or shift left + shift_out[7:1] <= shift_out[6:0]; + end end ssp_clk <= ~clock_cnt[3]; // ssp_clk frequency = 13,56MHz / 16 = 847,5 kHz diff --git a/fpga/hi_iso14443a.v b/fpga/hi_iso14443a.v index 182b66f7e..0ceac6d95 100644 --- a/fpga/hi_iso14443a.v +++ b/fpga/hi_iso14443a.v @@ -104,8 +104,6 @@ begin end end - - //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // Tag -> PM3 // filter the input for a tag's signal. The filter box needs the 4 previous input values and is a gaussian derivative filter @@ -132,7 +130,6 @@ wire [9:0] tmp2 = adc_d_times_2 + input_prev_1; // convert intermediate signals to signed and calculate the filter output wire signed [10:0] adc_d_filtered = {1'b0, tmp1} - {1'b0, tmp2}; - //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // internal FPGA timing. Maximum required period is 128 carrier clock cycles for a full 8 Bit transfer to ARM. (i.e. we need a // 7 bit counter). Adjust its frequency to external reader's clock when simulating a tag or sniffing. @@ -176,7 +173,6 @@ begin end end - //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // Tag -> PM3: // determine best possible time for starting/resetting the modulation detector. @@ -208,7 +204,6 @@ begin end end - //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // Tag -> PM3: // modulation detector. Looks for the steepest falling and rising edges within a 16 clock period. If there is both a significant @@ -228,27 +223,27 @@ always @(negedge adc_clk) begin if(negedge_cnt[3:0] == mod_detect_reset_time) begin - if (mod_type == `FPGA_HF_ISO14443A_SNIFFER) - begin - // detect modulation signal: if modulating, there must have been a falling AND a rising edge - if ((rx_mod_falling_edge_max > `EDGE_DETECT_THRESHOLDHIGH) && (rx_mod_rising_edge_max < -`EDGE_DETECT_THRESHOLDHIGH)) - curbit <= 1'b1; // modulation - else - curbit <= 1'b0; // no modulation - end - else - begin - // detect modulation signal: if modulating, there must have been a falling AND a rising edge - if ((rx_mod_falling_edge_max > `EDGE_DETECT_THRESHOLD) && (rx_mod_rising_edge_max < -`EDGE_DETECT_THRESHOLD)) - curbit <= 1'b1; // modulation - else - curbit <= 1'b0; // no modulation - end + if (mod_type == `FPGA_HF_ISO14443A_SNIFFER) + begin + // detect modulation signal: if modulating, there must have been a falling AND a rising edge + if ((rx_mod_falling_edge_max > `EDGE_DETECT_THRESHOLDHIGH) && (rx_mod_rising_edge_max < -`EDGE_DETECT_THRESHOLDHIGH)) + curbit <= 1'b1; // modulation + else + curbit <= 1'b0; // no modulation + end + else + begin + // detect modulation signal: if modulating, there must have been a falling AND a rising edge + if ((rx_mod_falling_edge_max > `EDGE_DETECT_THRESHOLD) && (rx_mod_rising_edge_max < -`EDGE_DETECT_THRESHOLD)) + curbit <= 1'b1; // modulation + else + curbit <= 1'b0; // no modulation + end // reset modulation detector rx_mod_rising_edge_max <= 0; rx_mod_falling_edge_max <= 0; end - else // look for steepest edges (slopes) + else // look for steepest edges (slopes) begin if (adc_d_filtered > 0) begin @@ -264,7 +259,6 @@ begin end - //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // Tag+Reader -> PM3 // sample 4 bits reader data and 4 bits tag data for sniffing @@ -280,7 +274,6 @@ begin end end - //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // PM3 -> Reader: // a delay line to ensure that we send the (emulated) tag's answer at the correct time according to ISO14443-3 @@ -303,7 +296,6 @@ begin end end - //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // PM3 -> Reader, internal timing: // a timer for the 1172 cycles fdt (Frame Delay Time). Start the timer with a rising edge of the reader's signal. @@ -366,7 +358,6 @@ begin if(fdt_counter == `FDT_INDICATOR_COUNT) fdt_indicator <= 1'b1; end - //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // PM3 -> Reader or Tag // assign a modulation signal to the antenna. This signal is either a delayed signal (to achieve fdt when sending to a reader) @@ -395,7 +386,6 @@ begin end end - //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // PM3 -> Reader // determine the required delay in the mod_sig_buf (set mod_sig_ptr). @@ -438,7 +428,6 @@ begin end end - //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // FPGA -> ARM communication: // buffer 8 bits data to be sent to ARM. Shift them out bit by bit. @@ -482,10 +471,8 @@ begin to_arm[7:1] <= to_arm[6:0]; end end - end - //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // FPGA <-> ARM communication: // generate a ssp clock and ssp frame signal for the synchronous transfer from/to the ARM @@ -520,7 +507,6 @@ begin end end - //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // FPGA -> ARM communication: // select the data to be sent to ARM @@ -565,7 +551,6 @@ assign sub_carrier = ~sub_carrier_cnt[3]; // in FPGA_HF_ISO14443A_READER_LISTEN: carrier always on; in other modes: carrier always off assign pwr_hi = (ck_1356meg & (((mod_type == `FPGA_HF_ISO14443A_READER_MOD) & ~mod_sig_coil) || (mod_type == `FPGA_HF_ISO14443A_READER_LISTEN))); - // Enable HF antenna drivers: assign pwr_oe1 = 1'b0; assign pwr_oe3 = 1'b0; diff --git a/fpga/hi_simulate.v b/fpga/hi_simulate.v index 2d8ff2771..77b9a44ed 100644 --- a/fpga/hi_simulate.v +++ b/fpga/hi_simulate.v @@ -88,7 +88,6 @@ begin end end - // Divide 13.56 MHz to produce various frequencies for SSP_CLK // and modulation. reg [8:0] ssp_clk_divider; @@ -99,17 +98,16 @@ always @(negedge adc_clk) always @(negedge adc_clk) begin if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K_8BIT) - // Get bit every at 53KHz (every 8th carrier bit of 424kHz) - ssp_clk <= ~ssp_clk_divider[7]; + // Get bit every at 53KHz (every 8th carrier bit of 424kHz) + ssp_clk <= ~ssp_clk_divider[7]; else if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K) - // Get next bit at 212kHz - ssp_clk <= ~ssp_clk_divider[5]; + // Get next bit at 212kHz + ssp_clk <= ~ssp_clk_divider[5]; else - // Get next bit at 424kHz - ssp_clk <= ~ssp_clk_divider[4]; + // Get next bit at 424kHz + ssp_clk <= ~ssp_clk_divider[4]; end - // Produce the byte framing signal; the phase of this signal // is arbitrary, because it's just a bit stream in this module. always @(negedge adc_clk) @@ -130,7 +128,6 @@ begin end end - // Synchronize up the after-hysteresis signal, to produce DIN. always @(posedge ssp_clk) ssp_din = after_hysteresis; @@ -147,9 +144,7 @@ always @(*) else if(mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K || mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K_8BIT) modulating_carrier <= ssp_dout & ssp_clk_divider[4]; // switch 424kHz modulation on/off else - modulating_carrier <= 1'b0; // yet unused - - + modulating_carrier <= 1'b0; // yet unused // Load modulation. Toggle only one of these, since we are already producing much deeper // modulation than a real tag would. diff --git a/fpga/lf_edge_detect.v b/fpga/lf_edge_detect.v index 1e4cd0cce..27d7f6901 100644 --- a/fpga/lf_edge_detect.v +++ b/fpga/lf_edge_detect.v @@ -1,4 +1,3 @@ - //----------------------------------------------------------------------------- // Copyright (C) Proxmark3 contributors. See AUTHORS.md for details. // @@ -30,73 +29,74 @@ module lf_edge_detect( output edge_toggle ); - min_max_tracker tracker( - .clk (clk), - .adc_d (adc_d), - .threshold (lf_ed_threshold), - .min (min), - .max (max) +min_max_tracker tracker( + .clk (clk), + .adc_d (adc_d), + .threshold (lf_ed_threshold), + .min (min), + .max (max) ); - // auto-tune - assign high_threshold = (max + min) / 2 + (max - min) / 4; - assign highz_threshold = (max + min) / 2 + (max - min) / 8; - assign lowz_threshold = (max + min) / 2 - (max - min) / 8; - assign low_threshold = (max + min) / 2 - (max - min) / 4; +// auto-tune +assign high_threshold = (max + min) / 2 + (max - min) / 4; +assign highz_threshold = (max + min) / 2 + (max - min) / 8; +assign lowz_threshold = (max + min) / 2 - (max - min) / 8; +assign low_threshold = (max + min) / 2 - (max - min) / 4; - // heuristic to see if it makes sense to try to detect an edge - wire enabled = - (high_threshold > highz_threshold) - & (highz_threshold > lowz_threshold) - & (lowz_threshold > low_threshold) - & ((high_threshold - highz_threshold) > 8) - & ((highz_threshold - lowz_threshold) > 16) - & ((lowz_threshold - low_threshold) > 8); +// heuristic to see if it makes sense to try to detect an edge +wire enabled = + (high_threshold > highz_threshold) + & (highz_threshold > lowz_threshold) + & (lowz_threshold > low_threshold) + & ((high_threshold - highz_threshold) > 8) + & ((highz_threshold - lowz_threshold) > 16) + & ((lowz_threshold - low_threshold) > 8); - // Toggle the output with hysteresis - // Set to high if the ADC value is above the threshold - // Set to low if the ADC value is below the threshold - reg is_high = 0; - reg is_low = 0; - reg is_zero = 0; - reg trigger_enabled = 1; - reg output_edge = 0; - reg output_state; +// Toggle the output with hysteresis +// Set to high if the ADC value is above the threshold +// Set to low if the ADC value is below the threshold +reg is_high = 0; +reg is_low = 0; +reg is_zero = 0; +reg trigger_enabled = 1; +reg output_edge = 0; +reg output_state; - always @(posedge clk) +always @(posedge clk) +begin + is_high <= (adc_d >= high_threshold); + is_low <= (adc_d <= low_threshold); + is_zero <= ((adc_d > lowz_threshold) & (adc_d < highz_threshold)); +end + +// all edges detection +always @(posedge clk) +if (enabled) +begin + // To enable detecting two consecutive peaks at the same level + // (low or high) we check whether or not we went back near 0 in-between. + // This extra check is necessary to prevent from noise artifacts + // around the threshold values. + if (trigger_enabled & (is_high | is_low)) begin - is_high <= (adc_d >= high_threshold); - is_low <= (adc_d <= low_threshold); - is_zero <= ((adc_d > lowz_threshold) & (adc_d < highz_threshold)); + output_edge <= ~output_edge; + trigger_enabled <= 0; end + else + trigger_enabled <= trigger_enabled | is_zero; +end - // all edges detection - always @(posedge clk) - if (enabled) - begin - // To enable detecting two consecutive peaks at the same level - // (low or high) we check whether or not we went back near 0 in-between. - // This extra check is necessary to prevent from noise artifacts - // around the threshold values. - if (trigger_enabled & (is_high | is_low)) - begin - output_edge <= ~output_edge; - trigger_enabled <= 0; - end else - trigger_enabled <= trigger_enabled | is_zero; - end +// edge states +always @(posedge clk) +if (enabled) +begin + if (is_high) + output_state <= 1'd1; + else if (is_low) + output_state <= 1'd0; +end - // edge states - always @(posedge clk) - if (enabled) - begin - if (is_high) - output_state <= 1'd1; - else if (is_low) - output_state <= 1'd0; - end - - assign edge_state = output_state; - assign edge_toggle = output_edge; +assign edge_state = output_state; +assign edge_toggle = output_edge; endmodule diff --git a/fpga/lo_edge_detect.v b/fpga/lo_edge_detect.v index 9bf408cc7..c29fdccb3 100644 --- a/fpga/lo_edge_detect.v +++ b/fpga/lo_edge_detect.v @@ -51,8 +51,8 @@ wire tag_modulation = ssp_dout & !lf_field; wire reader_modulation = !ssp_dout & lf_field & pck_divclk; // No logic, straight through. -assign pwr_oe1 = 1'b0; // not used in LF mode -assign pwr_oe3 = 1'b0; // base antenna load = 33 Ohms +assign pwr_oe1 = 1'b0; // not used in LF mode +assign pwr_oe3 = 1'b0; // base antenna load = 33 Ohms // when modulating, add another 33 Ohms and 10k Ohms in parallel: assign pwr_oe2 = tag_modulation; assign pwr_oe4 = tag_modulation; diff --git a/fpga/lo_read.v b/fpga/lo_read.v index 06bd0ae5a..c51857eb4 100644 --- a/fpga/lo_read.v +++ b/fpga/lo_read.v @@ -51,7 +51,7 @@ reg [7:0] to_arm_shiftreg; // we read the ADC value when pck_cnt=7 and shift it out on counts 8..15 always @(posedge pck0) begin - if((pck_cnt == 8'd7) && !pck_divclk) + if ((pck_cnt == 8'd7) && !pck_divclk) to_arm_shiftreg <= adc_d; else begin @@ -73,14 +73,15 @@ end // _ _ _ _ _ _ _ _ _ _ // ssp_clk |_| |_| |_| |_| |_| |_| |_| |_| |_| |_ -// serialized SSP data is gated by ant_lo to suppress unwanted signal +// serialized SSP data is gated by pck_divclk to suppress unwanted signal assign ssp_din = to_arm_shiftreg[7] && !pck_divclk; // SSP clock always runs at 24MHz assign ssp_clk = pck0; -// SSP frame is gated by ant_lo and goes high when pck_divider=8..15 +// SSP frame is gated by pck_divclk and goes high when pck_cnt=8..15 assign ssp_frame = (pck_cnt[7:3] == 5'd1) && !pck_divclk; // unused signals tied low assign pwr_hi = 1'b0; +// always on outputs, unused assign pwr_oe1 = 1'b0; assign pwr_oe2 = 1'b0; assign pwr_oe3 = 1'b0; diff --git a/fpga/min_max_tracker.v b/fpga/min_max_tracker.v index 2f6e06017..2aaab66bb 100644 --- a/fpga/min_max_tracker.v +++ b/fpga/min_max_tracker.v @@ -31,50 +31,50 @@ module min_max_tracker( output [7:0] max ); - reg [7:0] min_val = 255; - reg [7:0] max_val = 0; - reg [7:0] cur_min_val = 255; - reg [7:0] cur_max_val = 0; - reg [1:0] state = 0; +reg [7:0] min_val = 255; +reg [7:0] max_val = 0; +reg [7:0] cur_min_val = 255; +reg [7:0] cur_max_val = 0; +reg [1:0] state = 0; - always @(posedge clk) - begin - case (state) - 0: // initialize - begin - if (cur_max_val >= ({1'b0, adc_d} + threshold)) - state <= 2; - else if (adc_d >= ({1'b0, cur_min_val} + threshold)) - state <= 1; - if (cur_max_val <= adc_d) - cur_max_val <= adc_d; - else if (adc_d <= cur_min_val) - cur_min_val <= adc_d; +always @(posedge clk) +begin + case (state) + 0: // initialize + begin + if (cur_max_val >= ({1'b0, adc_d} + threshold)) + state <= 2; + else if (adc_d >= ({1'b0, cur_min_val} + threshold)) + state <= 1; + if (cur_max_val <= adc_d) + cur_max_val <= adc_d; + else if (adc_d <= cur_min_val) + cur_min_val <= adc_d; + end + 1: // high phase + begin + if (cur_max_val <= adc_d) + cur_max_val <= adc_d; + else if (({1'b0, adc_d} + threshold) <= cur_max_val) begin + state <= 2; + cur_min_val <= adc_d; + max_val <= cur_max_val; end - 1: // high phase - begin - if (cur_max_val <= adc_d) - cur_max_val <= adc_d; - else if (({1'b0, adc_d} + threshold) <= cur_max_val) begin - state <= 2; - cur_min_val <= adc_d; - max_val <= cur_max_val; - end + end + 2: // low phase + begin + if (adc_d <= cur_min_val) + cur_min_val <= adc_d; + else if (adc_d >= ({1'b0, cur_min_val} + threshold)) begin + state <= 1; + cur_max_val <= adc_d; + min_val <= cur_min_val; end - 2: // low phase - begin - if (adc_d <= cur_min_val) - cur_min_val <= adc_d; - else if (adc_d >= ({1'b0, cur_min_val} + threshold)) begin - state <= 1; - cur_max_val <= adc_d; - min_val <= cur_min_val; - end - end - endcase - end + end + endcase +end - assign min = min_val; - assign max = max_val; +assign min = min_val; +assign max = max_val; endmodule