Whitespace, formatting

fpga/clk_divider.v

@@ -22,7 +22,7 @@ module clk_divider(
 );
 
     reg [7:0] div_cnt_ = 0;
-    reg div_clk_;
+    reg div_clk_ = 0;
     assign div_cnt = div_cnt_;
     assign div_clk = div_clk_;
 

fpga/fpga_icopyx_lf.v

@@ -71,7 +71,13 @@ reg [7:0] lf_ed_threshold;
 wire [7:0] pck_cnt;
 wire pck_divclk;
 reg [7:0] divisor;
-clk_divider div_clk(pck0, divisor, pck_cnt, pck_divclk);
+
+clk_divider div_clk(
+    .clk     (pck0),
+    .divisor (divisor),
+    .div_cnt (pck_cnt),
+    .div_clk (pck_divclk)
+);
 
 // We switch modes between transmitting to the 13.56 MHz tag and receiving
 // from it, which means that we must make sure that we can do so without

fpga/hi_flite.v

@@ -144,7 +144,6 @@ reg[7:0] mid = 8'd128;
 // reg sending = 1'b0;  // are we actively modulating?
 reg [11:0] bit_counts = 12'd0; // for timeslots. only support ts=0 for now, at 212 speed  -512 fullbits from end of frame. One hopes.   might remove those?
 
-
 //we need some way to flush bit_counts triggers on mod_type changes don't compile
 reg dlay;
 always @(negedge adc_clk) // every data ping?
@@ -276,7 +275,6 @@ begin
         end
     end
 
-
     if (try_sync && tsinceedge < 128)
     begin
         //detect bits in their middle ssp sampling is in sync, so it would sample all bits in order
@@ -309,7 +307,6 @@ begin
                     mid <= 8'd127;
                 end
             end
-
         end
         else
         begin
@@ -340,9 +337,6 @@ begin
             end
         end
     end
-           else
-           begin
-            end
 //  sending <= 0;
 end
 

fpga/hi_get_trace.v

@@ -111,7 +111,6 @@ begin
     end
 end
 
-
 // (2+1)k RAM
 reg [7:0] D_out1, D_out2;
 reg [7:0] ram1 [2047:0]; // 2048  u8
@@ -135,7 +134,6 @@ begin
         D_out2 <= ram2[addr[9:0]];
 end
 
-
 reg [7:0] shift_out;
 
 always @(negedge ck_1356megb)

fpga/hi_iso14443a.v

@@ -104,8 +104,6 @@ begin
     end
 end
 
-
-
 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 // Tag -> PM3
 // filter the input for a tag's signal. The filter box needs the 4 previous input values and is a gaussian derivative filter
@@ -132,7 +130,6 @@ wire [9:0] tmp2 = adc_d_times_2 + input_prev_1;
 // convert intermediate signals to signed and calculate the filter output
 wire signed [10:0] adc_d_filtered = {1'b0, tmp1} - {1'b0, tmp2};
 
-
 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 // internal FPGA timing. Maximum required period is 128 carrier clock cycles for a full 8 Bit transfer to ARM. (i.e. we need a
 // 7 bit counter). Adjust its frequency to external reader's clock when simulating a tag or sniffing.
@@ -176,7 +173,6 @@ begin
     end
 end
 
-
 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 // Tag -> PM3:
 // determine best possible time for starting/resetting the modulation detector.
@@ -208,7 +204,6 @@ begin
     end
 end
 
-
 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 // Tag -> PM3:
 // modulation detector. Looks for the steepest falling and rising edges within a 16 clock period. If there is both a significant
@@ -264,7 +259,6 @@ begin
 
 end
 
-
 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 // Tag+Reader -> PM3
 // sample 4 bits reader data and 4 bits tag data for sniffing
@@ -280,7 +274,6 @@ begin
     end
 end
 
-
 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 // PM3 -> Reader:
 // a delay line to ensure that we send the (emulated) tag's answer at the correct time according to ISO14443-3
@@ -303,7 +296,6 @@ begin
     end
 end
 
-
 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 // PM3 -> Reader, internal timing:
 // a timer for the 1172 cycles fdt (Frame Delay Time). Start the timer with a rising edge of the reader's signal.
@@ -366,7 +358,6 @@ begin
     if(fdt_counter == `FDT_INDICATOR_COUNT) fdt_indicator <= 1'b1;
 end
 
-
 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 // PM3 -> Reader or Tag
 // assign a modulation signal to the antenna. This signal is either a delayed signal (to achieve fdt when sending to a reader)
@@ -395,7 +386,6 @@ begin
     end
 end
 
-
 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 // PM3 -> Reader
 // determine the required delay in the mod_sig_buf (set mod_sig_ptr).
@@ -438,7 +428,6 @@ begin
     end
 end
 
-
 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 // FPGA -> ARM communication:
 // buffer 8 bits data to be sent to ARM. Shift them out bit by bit.
@@ -482,10 +471,8 @@ begin
             to_arm[7:1] <= to_arm[6:0];
         end
     end
-
 end
 
-
 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 // FPGA <-> ARM communication:
 // generate a ssp clock and ssp frame signal for the synchronous transfer from/to the ARM
@@ -520,7 +507,6 @@ begin
     end
 end
 
-
 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 // FPGA -> ARM communication:
 // select the data to be sent to ARM
@@ -565,7 +551,6 @@ assign sub_carrier = ~sub_carrier_cnt[3];
 // in FPGA_HF_ISO14443A_READER_LISTEN: carrier always on; in other modes: carrier always off
 assign pwr_hi = (ck_1356meg & (((mod_type == `FPGA_HF_ISO14443A_READER_MOD) & ~mod_sig_coil) || (mod_type == `FPGA_HF_ISO14443A_READER_LISTEN)));
 
-
 // Enable HF antenna drivers:
 assign pwr_oe1 = 1'b0;
 assign pwr_oe3 = 1'b0;

fpga/hi_simulate.v

@@ -88,7 +88,6 @@ begin
     end
 end
 
-
 // Divide 13.56 MHz to produce various frequencies for SSP_CLK
 // and modulation.
 reg [8:0] ssp_clk_divider;
@@ -109,7 +108,6 @@ begin
         ssp_clk <= ~ssp_clk_divider[4];
 end
 
-
 // Produce the byte framing signal; the phase of this signal
 // is arbitrary, because it's just a bit stream in this module.
 always @(negedge adc_clk)
@@ -130,7 +128,6 @@ begin
     end
 end
 
-
 // Synchronize up the after-hysteresis signal, to produce DIN.
 always @(posedge ssp_clk)
     ssp_din = after_hysteresis;
@@ -149,8 +146,6 @@ always @(*)
     else
         modulating_carrier <= 1'b0;                          // yet unused
 
-
-
 // Load modulation. Toggle only one of these, since we are already producing much deeper
 // modulation than a real tag would.
 assign pwr_oe1 = 1'b0;                  // 33 Ohms Load

fpga/lf_edge_detect.v

@@ -1,4 +1,3 @@
-
 //-----------------------------------------------------------------------------
 // Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
 //
@@ -82,7 +81,8 @@ module lf_edge_detect(
     begin
         output_edge <= ~output_edge;
         trigger_enabled <= 0;
-        end else
+    end
+    else
         trigger_enabled <= trigger_enabled | is_zero;
 end
 

fpga/lo_read.v

@@ -73,14 +73,15 @@ end
 //         _   _   _   _   _   _   _   _   _   _
 // ssp_clk  |_| |_| |_| |_| |_| |_| |_| |_| |_| |_
 
-// serialized SSP data is gated by ant_lo to suppress unwanted signal
+// serialized SSP data is gated by pck_divclk to suppress unwanted signal
 assign ssp_din = to_arm_shiftreg[7] && !pck_divclk;
 // SSP clock always runs at 24MHz
 assign ssp_clk = pck0;
-// SSP frame is gated by ant_lo and goes high when pck_divider=8..15
+// SSP frame is gated by pck_divclk and goes high when pck_cnt=8..15
 assign ssp_frame = (pck_cnt[7:3] == 5'd1) && !pck_divclk;
 // unused signals tied low
 assign pwr_hi  = 1'b0;
+// always on outputs, unused
 assign pwr_oe1 = 1'b0;
 assign pwr_oe2 = 1'b0;
 assign pwr_oe3 = 1'b0;