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* Legic: rewrite reader to use xcorrelation and precise timing - Even tough Legic tags transmit just AM, receiving using xcorrelation results in a significantly better signal quality. - Switching from bit bang to a hardware based ssc frees up CPU time for other tasks e.g. prng and demodulation - Having all times based on a fixed ts, results in perfect rwd-tag synchronization without magic +/- calculations. * hi_read_tx: remove jerry-riged hysteresis based receiver - This feature got obsolete by a x-correlation based receiver. * Legic: adjusted sampling to new ssp clock speed - Sampling is 4 times faster and pipeline daly reduced to 1/4. The new code samples each bit earyler to account for the shorter pipeline. That introduced bit errors by leeking the next bit into the current one. * Legic: average 8 samples for better noise rejection. * Update CHANGELOG.md
78 lines
No EOL
1.9 KiB
Verilog
78 lines
No EOL
1.9 KiB
Verilog
//-----------------------------------------------------------------------------
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// The way that we connect things when transmitting a command to an ISO
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// 15693 tag, using 100% modulation only for now.
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//
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// Jonathan Westhues, April 2006
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//-----------------------------------------------------------------------------
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module hi_read_tx(
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pck0, ck_1356meg, ck_1356megb,
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pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
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adc_d, adc_clk,
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ssp_frame, ssp_din, ssp_dout, ssp_clk,
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cross_hi, cross_lo,
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dbg,
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shallow_modulation
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);
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input pck0, ck_1356meg, ck_1356megb;
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output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
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input [7:0] adc_d;
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output adc_clk;
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input ssp_dout;
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output ssp_frame, ssp_din, ssp_clk;
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input cross_hi, cross_lo;
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output dbg;
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input shallow_modulation;
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// low frequency outputs, not relevant
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assign pwr_lo = 1'b0;
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assign pwr_oe2 = 1'b0;
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// The high-frequency stuff. For now, for testing, just bring out the carrier,
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// and allow the ARM to modulate it over the SSP.
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reg pwr_hi;
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reg pwr_oe1;
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reg pwr_oe3;
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reg pwr_oe4;
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always @(ck_1356megb or ssp_dout or shallow_modulation)
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begin
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if(shallow_modulation)
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begin
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pwr_hi <= ck_1356megb;
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pwr_oe1 <= 1'b0;
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pwr_oe3 <= 1'b0;
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pwr_oe4 <= ~ssp_dout;
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end
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else
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begin
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pwr_hi <= ck_1356megb & ssp_dout;
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pwr_oe1 <= 1'b0;
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pwr_oe3 <= 1'b0;
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pwr_oe4 <= 1'b0;
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end
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end
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// Then just divide the 13.56 MHz clock down to produce appropriate clocks
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// for the synchronous serial port.
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reg [6:0] hi_div_by_128;
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always @(posedge ck_1356meg)
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hi_div_by_128 <= hi_div_by_128 + 1;
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assign ssp_clk = hi_div_by_128[6];
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reg [2:0] hi_byte_div;
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always @(negedge ssp_clk)
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hi_byte_div <= hi_byte_div + 1;
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assign ssp_frame = (hi_byte_div == 3'b000);
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assign ssp_din = 1'b0;
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assign dbg = ssp_frame;
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endmodule |