fpga/fpga_hf.v, fpga_lf.v, lo_edge_detect.v, lo_passthru.v, lo_read.v: copyright notice

This commit is contained in:
iZsh 2014-06-20 12:38:58 +02:00
parent 62638f87db
commit fa57f6e12e
5 changed files with 5 additions and 1 deletions

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@ -10,6 +10,7 @@
// //
// Jonathan Westhues, March 2006 // Jonathan Westhues, March 2006
// Added ISO14443-A support by Gerhard de Koning Gans, April 2008 // Added ISO14443-A support by Gerhard de Koning Gans, April 2008
// iZsh <izsh at fail0verflow.com>, June 2014
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
`include "hi_read_tx.v" `include "hi_read_tx.v"

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@ -9,7 +9,7 @@
// could be improved. // could be improved.
// //
// Jonathan Westhues, March 2006 // Jonathan Westhues, March 2006
// Added ISO14443-A support by Gerhard de Koning Gans, April 2008 // iZsh <izsh at fail0verflow.com>, June 2014
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
`include "lo_read.v" `include "lo_read.v"

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// (because it is so slow). // (because it is so slow).
// //
// Jonathan Westhues, April 2006 // Jonathan Westhues, April 2006
// iZsh <izsh at fail0verflow.com>, June 2014
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
module lo_edge_detect( module lo_edge_detect(

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@ -2,6 +2,7 @@
// For reading TI tags, we need to place the FPGA in pass through mode // For reading TI tags, we need to place the FPGA in pass through mode
// and pass everything through to the ARM // and pass everything through to the ARM
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
// iZsh <izsh at fail0verflow.com>, June 2014
module lo_passthru( module lo_passthru(
input pck_divclk, input pck_divclk,

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@ -4,6 +4,7 @@
// The A/D samples at that same rate and the result is serialized. // The A/D samples at that same rate and the result is serialized.
// //
// Jonathan Westhues, April 2006 // Jonathan Westhues, April 2006
// iZsh <izsh at fail0verflow.com>, June 2014
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
module lo_read( module lo_read(