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adjust lf simulation - fix one bug + attempt... (#369)

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... to speed up the loops waiting for carrier signal to go high or low
by only checking for a halt (button press or usbpol) every 1000th loop
iteration.
some users were experiencing modulating reactions to be too slow.
This commit is contained in:
marshmellow42 2017-08-08 15:08:59 -04:00 • committed by pwpiwi
parent 8cf533fd98
commit f2081c4356
1 changed files with 34 additions and 9 deletions
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31
armsrc/lfops.c
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@ -387,6 +387,7 @@ void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
int i; int i;
uint8_t *tab = BigBuf_get_addr(); uint8_t *tab = BigBuf_get_addr();
//note this may destroy the bigbuf so be sure this is called before now...
FpgaDownloadAndGo(FPGA_BITSTREAM_LF); FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT); FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
@ -401,13 +402,19 @@ void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
i = 0; i = 0;
for(;;) { for(;;) {
//wait until SSC_CLK goes HIGH //wait until SSC_CLK goes HIGH
int ii = 0;
while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) { while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
if(BUTTON_PRESS() || (usb_poll_validate_length() )) { //only check every 1000th time (usb_poll_validate_length on some systems was too slow)
if ( ii == 1000 ) {
if (BUTTON_PRESS() || usb_poll_validate_length() ) {
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
DbpString("Stopped"); DbpString("Stopped");
return; return;
} }
ii=0;
}
WDT_HIT(); WDT_HIT();
ii++;
} }
if (ledcontrol) if (ledcontrol)
LED_D_ON(); LED_D_ON();
@ -419,14 +426,20 @@ void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
if (ledcontrol) if (ledcontrol)
LED_D_OFF(); LED_D_OFF();
ii=0;
//wait until SSC_CLK goes LOW //wait until SSC_CLK goes LOW
while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) { while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
if(BUTTON_PRESS() || (usb_poll_validate_length() )) { //only check every 1000th time (usb_poll_validate_length on some systems was too slow)
DbpString("Stopped"); if ( ii == 1000 ) {
if (BUTTON_PRESS() || usb_poll_validate_length() ) {
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
DbpString("Stopped");
return; return;
} }
ii=0;
}
WDT_HIT(); WDT_HIT();
ii++;
} }
i++; i++;
@ -545,6 +558,9 @@ void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags"); DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
return; return;
} }
// set LF so we don't kill the bigbuf we are setting with simulation data.
FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
fc(0,&n); fc(0,&n);
// special start of frame marker containing invalid bit sequences // special start of frame marker containing invalid bit sequences
fc(8, &n); fc(8, &n); // invalid fc(8, &n); fc(8, &n); // invalid
@ -595,6 +611,9 @@ void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
uint8_t clk = arg2 & 0xFF; uint8_t clk = arg2 & 0xFF;
uint8_t invert = (arg2 >> 8) & 1; uint8_t invert = (arg2 >> 8) & 1;
// set LF so we don't kill the bigbuf we are setting with simulation data.
FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
for (i=0; i<size; i++){ for (i=0; i<size; i++){
if (BitStream[i] == invert){ if (BitStream[i] == invert){
fcAll(fcLow, &n, clk, &modCnt); fcAll(fcLow, &n, clk, &modCnt);
@ -670,6 +689,9 @@ void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
uint8_t separator = arg2 & 1; uint8_t separator = arg2 & 1;
uint8_t invert = (arg2 >> 8) & 1; uint8_t invert = (arg2 >> 8) & 1;
// set LF so we don't kill the bigbuf we are setting with simulation data.
FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
if (encoding==2){ //biphase if (encoding==2){ //biphase
uint8_t phase=0; uint8_t phase=0;
for (i=0; i<size; i++){ for (i=0; i<size; i++){
@ -741,6 +763,9 @@ void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
uint8_t carrier = arg1 & 0xFF; uint8_t carrier = arg1 & 0xFF;
uint8_t invert = arg2 & 0xFF; uint8_t invert = arg2 & 0xFF;
uint8_t curPhase = 0; uint8_t curPhase = 0;
// set LF so we don't kill the bigbuf we are setting with simulation data.
FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
for (i=0; i<size; i++){ for (i=0; i<size; i++){
if (BitStream[i] == curPhase){ if (BitStream[i] == curPhase){
pskSimBit(carrier, &n, clk, &curPhase, FALSE); pskSimBit(carrier, &n, clk, &curPhase, FALSE);