Legic: rewrite reader to use xcorrelation and precise timing (#654)

* Legic: rewrite reader to use xcorrelation and precise timing
 - Even tough Legic tags transmit just AM, receiving using
   xcorrelation results in a significantly better signal
   quality.
 - Switching from bit bang to a hardware based ssc frees
   up CPU time for other tasks e.g. prng and demodulation
 - Having all times based on a fixed ts, results in perfect
   rwd-tag synchronization without magic +/- calculations.
* hi_read_tx: remove jerry-riged hysteresis based receiver
- This feature got obsolete by a x-correlation based receiver.
* Legic: adjusted sampling to new ssp clock speed
- Sampling is 4 times faster and pipeline daly reduced to 1/4.
 The new code samples each bit earyler to account for the
 shorter pipeline. That introduced bit errors by leeking the
 next bit into the current one.
* Legic: average 8 samples for better noise rejection.
* Update CHANGELOG.md

fpga/hi_read_tx.v

@@ -71,21 +71,8 @@ always @(negedge ssp_clk)
 
 assign ssp_frame = (hi_byte_div == 3'b000);
 
-// Implement a hysteresis to give out the received signal on
-// ssp_din. Sample at fc.
-assign adc_clk = ck_1356meg;
+assign ssp_din = 1'b0;
 
-// ADC data appears on the rising edge, so sample it on the falling edge
-reg after_hysteresis;
-always @(negedge adc_clk)
-begin
-    if(& adc_d[7:0]) after_hysteresis <= 1'b1;
-    else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;
-end
+assign dbg = ssp_frame;
 
-
-assign ssp_din = after_hysteresis;
-
-assign dbg = ssp_din;
-
-endmodule
+endmodule