diff --git a/armsrc/Makefile b/armsrc/Makefile index bc15aeb9..d73f2e77 100644 --- a/armsrc/Makefile +++ b/armsrc/Makefile @@ -2,24 +2,29 @@ APP_INCLUDES = apps.h -# Add the "-DWITH_LCD" flag in APP_CLFAGS to add support for LCD -# and add SRC_LCD to THUMBSRC -APP_CFLAGS = -O6 +#remove one of the following defines and comment out the relevant line +#in the next section to remove that particular feature from compilation +APP_CFLAGS = -O6 -DWITH_ISO15693 -DWITH_ISO14443a -DWITH_ISO14443b +#-DWITH_LCD -SRC_LCD = fonts.c LCD.c +#SRC_LCD = fonts.c LCD.c +SRC_ISO15693 = iso15693.c +SRC_ISO14443a = iso14443a.c +SRC_ISO14443b = iso14443.c THUMBSRC = start.c \ + $(SRC_LCD) \ + $(SRC_ISO15693) \ appmain.c \ lfops.c \ - iso15693.c \ util.c \ hitag2.c \ usb.c # These are to be compiled in ARM mode -ARMSRC = iso14443.c \ - iso14443a.c \ - fpgaloader.c +ARMSRC = fpgaloader.c \ + $(SRC_ISO14443a) \ + $(SRC_ISO14443b) # Do not move this inclusion before the definition of {THUMB,ASM,ARM}SRC include ../common/Makefile.common diff --git a/armsrc/fpgaloader.c b/armsrc/fpgaloader.c index 8cea61b0..af2f02ab 100644 --- a/armsrc/fpgaloader.c +++ b/armsrc/fpgaloader.c @@ -152,28 +152,50 @@ static void DownloadFPGA_byte(unsigned char w) // If bytereversal is set: reverse the byte order in each 4-byte word static void DownloadFPGA(const char *FpgaImage, int FpgaImageLen, int bytereversal) { - int i; + int i=0; PIO_OUTPUT_ENABLE = (1 << GPIO_FPGA_ON); PIO_ENABLE = (1 << GPIO_FPGA_ON); - PIO_OUTPUT_DATA_SET = (1 << GPIO_FPGA_ON); + HIGH(GPIO_FPGA_ON); // ensure everything is powered on SpinDelay(50); LED_D_ON(); + // These pins are inputs + PIO_OUTPUT_DISABLE = (1 << GPIO_FPGA_NINIT) | (1 << GPIO_FPGA_DONE); + // PIO controls the following pins + PIO_ENABLE = (1 << GPIO_FPGA_NINIT) | (1 << GPIO_FPGA_DONE); + // Enable pull-ups + PIO_NO_PULL_UP_DISABLE = (1 << GPIO_FPGA_NINIT) | (1 << GPIO_FPGA_DONE); + + // setup initial logic state HIGH(GPIO_FPGA_NPROGRAM); LOW(GPIO_FPGA_CCLK); LOW(GPIO_FPGA_DIN); + // These pins are outputs PIO_OUTPUT_ENABLE = (1 << GPIO_FPGA_NPROGRAM) | (1 << GPIO_FPGA_CCLK) | (1 << GPIO_FPGA_DIN); - SpinDelay(1); + // enter FPGA configuration mode LOW(GPIO_FPGA_NPROGRAM); SpinDelay(50); HIGH(GPIO_FPGA_NPROGRAM); + i=100000; + // wait for FPGA ready to accept data signal + while ((i) && ( !(PIO_PIN_DATA_STATUS & (1<