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https://github.com/Proxmark/proxmark3.git
synced 2025-08-21 05:43:23 -07:00
new command "lf snoop" to snoop raw ADC values
fpga/lo_read.v (lf_field): new argument. fpga/fpga_lf.v: modify accordingly. armsrc/apps.h (FPGA_MAJOR_MODE_LF_READER): Rename as FPGA_MAJOR_MODE_LF_ADC. armsrc/apps.h (FPGA_LF_ADC_READER_FIELD): New LF option. armsrc/lfops.c: Modify accordingly. client/cmdlf.c (CmdLFSnoop): New command. armsrc/appmain.c, armsrc/lfops.c, client/cmdlf.h, include/usb_cmd.h: Modify accordingly.
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9 changed files with 75 additions and 32 deletions
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@ -215,7 +215,7 @@ void MeasureAntennaTuning(void)
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*/
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FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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for (i=255; i>19; i--) {
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WDT_HIT();
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, i);
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@ -638,6 +638,10 @@ void UsbPacketReceived(uint8_t *packet, int len)
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case CMD_MOD_THEN_ACQUIRE_RAW_ADC_SAMPLES_125K:
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ModThenAcquireRawAdcSamples125k(c->arg[0],c->arg[1],c->arg[2],c->d.asBytes);
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break;
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case CMD_LF_SNOOP_RAW_ADC_SAMPLES:
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SnoopLFRawAdcSamples(c->arg[0], c->arg[1]);
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cmd_send(CMD_ACK,0,0,0,0,0);
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break;
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case CMD_HID_DEMOD_FSK:
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CmdHIDdemodFSK(0, 0, 0, 1); // Demodulate HID tag
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break;
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@ -59,7 +59,8 @@ void ToSendStuffBit(int b);
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void ToSendReset(void);
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void ListenReaderField(int limit);
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void AcquireRawAdcSamples125k(int at134khz);
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void DoAcquisition125k(void);
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void SnoopLFRawAdcSamples(int divisor, int trigger_threshold);
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void DoAcquisition125k(int trigger_threshold);
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extern int ToSendMax;
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extern uint8_t ToSend[];
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extern uint32_t BigBuf[];
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@ -82,8 +83,8 @@ void SetAdcMuxFor(uint32_t whichGpio);
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#define FPGA_CMD_SET_DIVISOR (2<<12)
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// Definitions for the FPGA configuration word.
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// LF
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#define FPGA_MAJOR_MODE_LF_READER (0<<5)
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#define FPGA_MAJOR_MODE_LF_EDGE_DETECT (1<<5)
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#define FPGA_MAJOR_MODE_LF_ADC (0<<5)
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#define FPGA_MAJOR_MODE_LF_EDGE_DETECT (1<<5)
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#define FPGA_MAJOR_MODE_LF_PASSTHRU (2<<5)
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// HF
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#define FPGA_MAJOR_MODE_HF_READER_TX (0<<5)
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@ -92,6 +93,8 @@ void SetAdcMuxFor(uint32_t whichGpio);
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#define FPGA_MAJOR_MODE_HF_ISO14443A (3<<5)
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// BOTH
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#define FPGA_MAJOR_MODE_OFF (7<<5)
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// Options for LF_ADC
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#define FPGA_LF_ADC_READER_FIELD (1<<0)
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// Options for LF_EDGE_DETECT
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#define FPGA_LF_EDGE_DETECT_READER_FIELD (1<<0)
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// Options for the HF reader, tx to tag
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@ -15,7 +15,7 @@
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#include "crc16.h"
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#include "string.h"
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void AcquireRawAdcSamples125k(int divisor)
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void LFSetupFPGAForADC(int divisor, bool lf_field)
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{
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FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
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if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
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@ -25,23 +25,30 @@ void AcquireRawAdcSamples125k(int divisor)
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else
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0));
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// Connect the A/D to the peak-detected low-frequency path.
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SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
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// Give it a bit of time for the resonant antenna to settle.
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SpinDelay(50);
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// Now set up the SSC to get the ADC samples that are now streaming at us.
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FpgaSetupSsc();
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}
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// Now call the acquisition routine
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DoAcquisition125k();
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void AcquireRawAdcSamples125k(int divisor)
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{
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LFSetupFPGAForADC(divisor, true);
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DoAcquisition125k(-1);
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}
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void SnoopLFRawAdcSamples(int divisor, int trigger_threshold)
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{
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LFSetupFPGAForADC(divisor, false);
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DoAcquisition125k(trigger_threshold);
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}
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// split into two routines so we can avoid timing issues after sending commands //
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void DoAcquisition125k(void)
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void DoAcquisition125k(int trigger_threshold)
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{
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uint8_t *dest = (uint8_t *)BigBuf;
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int n = sizeof(BigBuf);
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@ -56,9 +63,12 @@ void DoAcquisition125k(void)
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}
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if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
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dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
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i++;
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LED_D_OFF();
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if (i >= n) break;
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if (trigger_threshold != -1 && dest[i] < trigger_threshold)
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continue;
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else
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trigger_threshold = -1;
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if (++i >= n) break;
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}
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}
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Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
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@ -85,7 +95,7 @@ void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1,
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else
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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// Give it a bit of time for the resonant antenna to settle.
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SpinDelay(50);
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@ -105,7 +115,7 @@ void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1,
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else
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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LED_D_ON();
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if(*(command++) == '0')
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SpinDelayUs(period_0);
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@ -120,10 +130,10 @@ void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1,
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else
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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// now do the read
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DoAcquisition125k();
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DoAcquisition125k(-1);
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}
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/* blank r/w tag data stream
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@ -609,7 +619,7 @@ void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
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FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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// Connect the A/D to the peak-detected low-frequency path.
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SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
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@ -823,7 +833,7 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
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FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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// Connect the A/D to the peak-detected low-frequency path.
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SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
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@ -1141,7 +1151,7 @@ void T55xxWriteBit(int bit)
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{
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FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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if (bit == 0)
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SpinDelayUs(WRITE_0);
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else
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@ -1157,7 +1167,7 @@ void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMod
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FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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// Give it a bit of time for the resonant antenna to settle.
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// And for the tag to fully power up
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@ -1189,7 +1199,7 @@ void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMod
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// Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
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// so wait a little more)
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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SpinDelay(20);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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}
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@ -1211,7 +1221,7 @@ void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
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LED_D_ON();
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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// Give it a bit of time for the resonant antenna to settle.
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// And for the tag to fully power up
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@ -1237,7 +1247,7 @@ void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
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// Turn field on to read the response
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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// Now do the acquisition
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i = 0;
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@ -1276,7 +1286,7 @@ void T55xxReadTrace(void){
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LED_D_ON();
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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// Give it a bit of time for the resonant antenna to settle.
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// And for the tag to fully power up
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@ -1292,7 +1302,7 @@ void T55xxReadTrace(void){
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// Turn field on to read the response
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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// Now do the acquisition
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i = 0;
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@ -1983,7 +1993,7 @@ void SendForward(uint8_t fwd_bit_count) {
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//Field on
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FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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// Give it a bit of time for the resonant antenna to settle.
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// And for the tag to fully power up
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@ -1995,7 +2005,7 @@ void SendForward(uint8_t fwd_bit_count) {
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
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SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);//field on
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
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SpinDelayUs(16*8); //16 cycles on (8us each)
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// now start writting
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@ -2007,7 +2017,7 @@ void SendForward(uint8_t fwd_bit_count) {
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
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SpinDelayUs(23*8); //16-4 cycles off (8us each)
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);//field on
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
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SpinDelayUs(9*8); //16 cycles on (8us each)
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}
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}
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