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This commit is contained in:
Martin Holst Swende 2014-06-07 22:04:27 +02:00
commit 94ad01bfba
4 changed files with 43 additions and 33 deletions
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1
armsrc/apps.h
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@ -100,6 +100,7 @@ void SetAdcMuxFor(uint32_t whichGpio);
#define FPGA_HF_SIMULATOR_NO_MODULATION (0<<0) #define FPGA_HF_SIMULATOR_NO_MODULATION (0<<0)
#define FPGA_HF_SIMULATOR_MODULATE_BPSK (1<<0) #define FPGA_HF_SIMULATOR_MODULATE_BPSK (1<<0)
#define FPGA_HF_SIMULATOR_MODULATE_212K (2<<0) #define FPGA_HF_SIMULATOR_MODULATE_212K (2<<0)
#define FPGA_HF_SIMULATOR_MODULATE_424K (4<<0)
// Options for ISO14443A // Options for ISO14443A
#define FPGA_HF_ISO14443A_SNIFFER (0<<0) #define FPGA_HF_ISO14443A_SNIFFER (0<<0)
#define FPGA_HF_ISO14443A_TAGSIM_LISTEN (1<<0) #define FPGA_HF_ISO14443A_TAGSIM_LISTEN (1<<0)

68
armsrc/iclass.c
View file

@ -1090,6 +1090,12 @@ int doIClassSimulation(uint8_t csn[], int breakAfterMacReceived)
CodeIClassTagAnswer(response4, sizeof(response4)); CodeIClassTagAnswer(response4, sizeof(response4));
memcpy(resp4, ToSend, ToSendMax); resp4Len = ToSendMax; memcpy(resp4, ToSend, ToSendMax); resp4Len = ToSendMax;
// Start from off (no field generated)
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
SpinDelay(200);
// We need to listen to the high-frequency, peak-detected path. // We need to listen to the high-frequency, peak-detected path.
SetAdcMuxFor(GPIO_MUXSEL_HIPKD); SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
FpgaSetupSsc(); FpgaSetupSsc();
@ -1107,11 +1113,17 @@ int doIClassSimulation(uint8_t csn[], int breakAfterMacReceived)
displayDebug = true; displayDebug = true;
LED_B_OFF(); LED_B_OFF();
//Signal tracer
// Can be used to get a trigger for an oscilloscope..
LED_C_OFF();
if(!GetIClassCommandFromReader(receivedCmd, &len, 100)) { if(!GetIClassCommandFromReader(receivedCmd, &len, 100)) {
buttonPressed = true; buttonPressed = true;
break; break;
} }
r2t_time = GetCountSspClk(); r2t_time = GetCountSspClk();
//Signal tracer
LED_C_ON();
// Okay, look at the command now. // Okay, look at the command now.
if(receivedCmd[0] == 0x0a ) { if(receivedCmd[0] == 0x0a ) {
@ -1236,41 +1248,34 @@ int doIClassSimulation(uint8_t csn[], int breakAfterMacReceived)
static int SendIClassAnswer(uint8_t *resp, int respLen, int delay) static int SendIClassAnswer(uint8_t *resp, int respLen, int delay)
{ {
int i = 0, u = 0, d = 0; int i = 0, d=0;//, u = 0, d = 0;
uint8_t b = 0; uint8_t b = 0;
// return 0;
// Modulate Manchester FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR|FPGA_HF_SIMULATOR_MODULATE_424K);
// FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD424);
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
AT91C_BASE_SSC->SSC_THR = 0x00; AT91C_BASE_SSC->SSC_THR = 0x00;
FpgaSetupSsc(); FpgaSetupSsc();
while(!BUTTON_PRESS()) {
// send cycle if((AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY)){
for(;;) { b = AT91C_BASE_SSC->SSC_RHR; (void) b;
if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
volatile uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
(void)b;
} }
if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)){
b = 0x00;
if(d < delay) { if(d < delay) {
b = 0x00;
d++; d++;
} }
else if(i >= respLen) { else {
b = 0x00; if( i < respLen){
u++; b = resp[i];
} else { //Hack
b = resp[i]; //b = 0xAC;
u++; }
if(u > 1) { i++; u = 0; } i++;
} }
AT91C_BASE_SSC->SSC_THR = b; AT91C_BASE_SSC->SSC_THR = b;
}
if(u > 4) break; if (i > respLen +4) break;
}
if(BUTTON_PRESS()) {
break;
}
} }
return 0; return 0;
@ -1284,7 +1289,6 @@ static int SendIClassAnswer(uint8_t *resp, int respLen, int delay)
static void TransmitIClassCommand(const uint8_t *cmd, int len, int *samples, int *wait) static void TransmitIClassCommand(const uint8_t *cmd, int len, int *samples, int *wait)
{ {
int c; int c;
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD); FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
AT91C_BASE_SSC->SSC_THR = 0x00; AT91C_BASE_SSC->SSC_THR = 0x00;
FpgaSetupSsc(); FpgaSetupSsc();
@ -1360,12 +1364,12 @@ void CodeIClassCommand(const uint8_t * cmd, int len)
b = cmd[i]; b = cmd[i];
for(j = 0; j < 4; j++) { for(j = 0; j < 4; j++) {
for(k = 0; k < 4; k++) { for(k = 0; k < 4; k++) {
if(k == (b & 3)) { if(k == (b & 3)) {
ToSend[++ToSendMax] = 0x0f; ToSend[++ToSendMax] = 0x0f;
} }
else { else {
ToSend[++ToSendMax] = 0x00; ToSend[++ToSendMax] = 0x00;
} }
} }
b >>= 2; b >>= 2;
} }

BIN
fpga/fpga.bit
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7
fpga/hi_simulate.v
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@ -89,7 +89,9 @@ always @(mod_type or ssp_clk or ssp_dout)
else if(mod_type == 3'b001) else if(mod_type == 3'b001)
modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK
else if(mod_type == 3'b010) else if(mod_type == 3'b010)
modulating_carrier <= ssp_dout & ssp_clk_divider[5]; // switch 212kHz subcarrier on/off modulating_carrier <= ssp_dout & ssp_clk_divider[5]; // switch 212kHz subcarrier on/off
else if(mod_type == 3'b100)
modulating_carrier <= ssp_dout & ssp_clk_divider[4]; // switch 424kHz modulation on/off
else else
modulating_carrier <= 1'b0; // yet unused modulating_carrier <= 1'b0; // yet unused
@ -105,5 +107,8 @@ assign pwr_oe4 = modulating_carrier;
assign pwr_oe3 = 1'b0; assign pwr_oe3 = 1'b0;
assign dbg = after_hysteresis; assign dbg = after_hysteresis;
//reg dbg;
//always @(ssp_dout)
// dbg <= ssp_dout;
endmodule endmodule