From 883cc3fd376b720adf300b921f949d654c9e76dc Mon Sep 17 00:00:00 2001 From: AntiCat Date: Wed, 5 Sep 2018 22:45:59 +0200 Subject: [PATCH] FPGA Hi-Simulate: Fixed documantation --- fpga/hi_simulate.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/fpga/hi_simulate.v b/fpga/hi_simulate.v index 3976de93..65b61d6a 100644 --- a/fpga/hi_simulate.v +++ b/fpga/hi_simulate.v @@ -51,8 +51,8 @@ begin end -// Divide 13.56 MHz by 32 to produce the SSP_CLK -// The register is bigger to allow higher division factors of up to /128 +// Divide 13.56 MHz to produce various frequencies for SSP_CLK +// and modulation. 11 bits allow for factors of up to /128. reg [10:0] ssp_clk_divider; always @(posedge adc_clk) @@ -106,7 +106,7 @@ reg ssp_din; always @(posedge ssp_clk) ssp_din = after_hysteresis; -// Modulating carrier frequency is fc/16, reuse ssp_clk divider for that +// Modulating carrier frequency is fc/64 (212kHz) to fc/16 (848kHz). Reuse ssp_clk divider for that. reg modulating_carrier; always @(mod_type or ssp_clk or ssp_dout) if(mod_type == 3'b000)