mirror of
https://github.com/Proxmark/proxmark3.git
synced 2025-08-14 02:26:59 -07:00
fixing some fpga and iclass issues
* make fpga_version_info.c phony and delete it on 'make clean' * wait for transfer to complete before returning from FpgaSendCommand() * log correct tag times in iclass simulation * shorten pulse from TC1 to TC0 in StartCountSspClk() * shorten ssp_frame pulse in fpga/hi_reader.v * some reformatting and whitespace fixes
This commit is contained in:
pwpiwi
parent
bedae7768c
commit
7a53739728
11 changed files with 170 additions and 184 deletions
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@ -83,8 +83,9 @@ all: $(OBJS)
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.DELETE_ON_ERROR:
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# version.c should be remade on every compilation
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.PHONY: version.c
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# version.c and fpga_version_info.c to be remade on every compilation
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.PHONY: version.c fpga_version_info.c
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version.c: default_version.c
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perl ../tools/mkversion.pl .. > $@ || $(COPY) $^ $@
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@ -132,7 +133,7 @@ clean:
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$(DELETE) $(OBJDIR)$(PATHSEP)*.d
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$(DELETE) $(OBJDIR)$(PATHSEP)*.z
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$(DELETE) $(OBJDIR)$(PATHSEP)*.bin
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$(DELETE) version.c
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$(DELETE) version.c fpga_version_info.c
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.PHONY: all clean help
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help:
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@ -1467,13 +1467,13 @@ void __attribute__((noreturn)) AppMain(void) {
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// Reset SPI
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AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST;
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AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST; // required twice on some AT91SAM Revisions (see Errata in AT91SAM datasheet)
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// Reset SSC
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AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
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// Load the FPGA image, which we have stored in our flash.
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// (the HF version by default)
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// Load the FPGA image, which we have stored in our flash (HF version by default)
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FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
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StartTickCount();
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#ifdef WITH_LCD
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@ -32,7 +32,7 @@ extern uint8_t _binary_obj_fpga_all_bit_z_start, _binary_obj_fpga_all_bit_z_end;
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static uint8_t *fpga_image_ptr = NULL;
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static uint32_t uncompressed_bytes_cnt;
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#define OUTPUT_BUFFER_LEN 80
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#define OUTPUT_BUFFER_LEN 80
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//-----------------------------------------------------------------------------
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// Set up the Serial Peripheral Interface as master
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@ -49,16 +49,16 @@ void SetupSpi(int mode)
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// Disable PIO control of the following pins, allows use by the SPI peripheral
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AT91C_BASE_PIOA->PIO_PDR =
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GPIO_NCS0 |
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GPIO_NCS2 |
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GPIO_MISO |
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GPIO_MOSI |
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GPIO_NCS0 |
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GPIO_NCS2 |
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GPIO_MISO |
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GPIO_MOSI |
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GPIO_SPCK;
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AT91C_BASE_PIOA->PIO_ASR =
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GPIO_NCS0 |
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GPIO_MISO |
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GPIO_MOSI |
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GPIO_NCS0 |
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GPIO_MISO |
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GPIO_MOSI |
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GPIO_SPCK;
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AT91C_BASE_PIOA->PIO_BSR = GPIO_NCS2;
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@ -71,41 +71,41 @@ void SetupSpi(int mode)
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switch (mode) {
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case SPI_FPGA_MODE:
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AT91C_BASE_SPI->SPI_MR =
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( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods)
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(14 << 16) | // Peripheral Chip Select (selects FPGA SPI_NCS0 or PA11)
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( 0 << 7) | // Local Loopback Disabled
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( 1 << 4) | // Mode Fault Detection disabled
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( 0 << 2) | // Chip selects connected directly to peripheral
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( 0 << 1) | // Fixed Peripheral Select
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( 1 << 0); // Master Mode
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( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods)
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(14 << 16) | // Peripheral Chip Select (selects FPGA SPI_NCS0 or PA11)
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( 0 << 7) | // Local Loopback Disabled
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( 1 << 4) | // Mode Fault Detection disabled
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( 0 << 2) | // Chip selects connected directly to peripheral
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( 0 << 1) | // Fixed Peripheral Select
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( 1 << 0); // Master Mode
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AT91C_BASE_SPI->SPI_CSR[0] =
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( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)
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( 1 << 16) | // Delay Before SPCK (1 MCK period)
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( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
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( 8 << 4) | // Bits per Transfer (16 bits)
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( 0 << 3) | // Chip Select inactive after transfer
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( 1 << 1) | // Clock Phase data captured on leading edge, changes on following edge
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( 0 << 0); // Clock Polarity inactive state is logic 0
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( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)
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( 1 << 16) | // Delay Before SPCK (1 MCK period)
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( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
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( 8 << 4) | // Bits per Transfer (16 bits)
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( 0 << 3) | // Chip Select inactive after transfer
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( 1 << 1) | // Clock Phase data captured on leading edge, changes on following edge
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( 0 << 0); // Clock Polarity inactive state is logic 0
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break;
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case SPI_LCD_MODE:
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AT91C_BASE_SPI->SPI_MR =
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( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods)
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(11 << 16) | // Peripheral Chip Select (selects LCD SPI_NCS2 or PA10)
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( 0 << 7) | // Local Loopback Disabled
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( 1 << 4) | // Mode Fault Detection disabled
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( 0 << 2) | // Chip selects connected directly to peripheral
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( 0 << 1) | // Fixed Peripheral Select
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( 1 << 0); // Master Mode
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( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods)
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(11 << 16) | // Peripheral Chip Select (selects LCD SPI_NCS2 or PA10)
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( 0 << 7) | // Local Loopback Disabled
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( 1 << 4) | // Mode Fault Detection disabled
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( 0 << 2) | // Chip selects connected directly to peripheral
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( 0 << 1) | // Fixed Peripheral Select
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( 1 << 0); // Master Mode
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AT91C_BASE_SPI->SPI_CSR[2] =
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( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)
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( 1 << 16) | // Delay Before SPCK (1 MCK period)
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( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
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( 1 << 4) | // Bits per Transfer (9 bits)
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( 0 << 3) | // Chip Select inactive after transfer
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( 1 << 1) | // Clock Phase data captured on leading edge, changes on following edge
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( 0 << 0); // Clock Polarity inactive state is logic 0
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( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)
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( 1 << 16) | // Delay Before SPCK (1 MCK period)
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( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
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( 1 << 4) | // Bits per Transfer (9 bits)
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( 0 << 3) | // Chip Select inactive after transfer
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( 1 << 1) | // Clock Phase data captured on leading edge, changes on following edge
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( 0 << 0); // Clock Polarity inactive state is logic 0
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break;
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default: // Disable SPI
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default: // Disable SPI
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AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIDIS;
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break;
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}
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@ -118,9 +118,9 @@ void SetupSpi(int mode)
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void FpgaSetupSsc(uint16_t FPGA_mode) {
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// First configure the GPIOs, and get ourselves a clock.
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AT91C_BASE_PIOA->PIO_ASR =
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GPIO_SSC_FRAME |
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GPIO_SSC_DIN |
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GPIO_SSC_DOUT |
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GPIO_SSC_FRAME |
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GPIO_SSC_DIN |
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GPIO_SSC_DOUT |
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GPIO_SSC_CLK;
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AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
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@ -135,14 +135,14 @@ void FpgaSetupSsc(uint16_t FPGA_mode) {
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// 8, 16 or 32 bits per transfer, no loopback, MSB first, 1 transfer per sync
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// pulse, no output sync
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if ((FPGA_mode & 0x1c0) == FPGA_MAJOR_MODE_HF_READER && FpgaGetCurrent() == FPGA_BITSTREAM_HF) {
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if ((FPGA_mode & FPGA_MAJOR_MODE_MASK) == FPGA_MAJOR_MODE_HF_READER && FpgaGetCurrent() == FPGA_BITSTREAM_HF) {
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AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(16) | AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
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} else {
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AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) | AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
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}
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}
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// TX clock comes from TK pin, no clock output, outputs change on falling
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// edge of TK, frame sync is sampled on rising edge of TK, start TX on rising edge of TF
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// TX clock comes from TK pin, no clock output, outputs change on rising edge of TK,
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// TF (frame sync) is sampled on falling edge of TK, start TX on rising edge of TF
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AT91C_BASE_SSC->SSC_TCMR = SSC_CLOCK_MODE_SELECT(2) | SSC_CLOCK_MODE_START(5);
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// tx framing is the same as the rx framing
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@ -157,8 +157,7 @@ void FpgaSetupSsc(uint16_t FPGA_mode) {
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// ourselves, not to another buffer). The stuff to manipulate those buffers
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// is in apps.h, because it should be inlined, for speed.
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//-----------------------------------------------------------------------------
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bool FpgaSetupSscDma(uint8_t *buf, uint16_t sample_count)
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{
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bool FpgaSetupSscDma(uint8_t *buf, uint16_t sample_count) {
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if (buf == NULL) return false;
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AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS; // Disable DMA Transfer
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@ -173,11 +172,11 @@ bool FpgaSetupSscDma(uint8_t *buf, uint16_t sample_count)
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//----------------------------------------------------------------------------
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// Uncompress (inflate) the FPGA data. Returns one decompressed byte with
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// each call.
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// each call.
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//----------------------------------------------------------------------------
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static int get_from_fpga_combined_stream(z_streamp compressed_fpga_stream, uint8_t *output_buffer)
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{
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if (fpga_image_ptr == compressed_fpga_stream->next_out) { // need more data
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if (fpga_image_ptr == compressed_fpga_stream->next_out) { // need more data
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compressed_fpga_stream->next_out = output_buffer;
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compressed_fpga_stream->avail_out = OUTPUT_BUFFER_LEN;
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fpga_image_ptr = output_buffer;
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@ -190,7 +189,7 @@ static int get_from_fpga_combined_stream(z_streamp compressed_fpga_stream, uint8
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}
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uncompressed_bytes_cnt++;
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return *fpga_image_ptr++;
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}
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@ -207,7 +206,7 @@ static int get_from_fpga_stream(int bitstream_version, z_streamp compressed_fpga
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}
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return get_from_fpga_combined_stream(compressed_fpga_stream, output_buffer);
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}
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@ -224,14 +223,14 @@ static void fpga_inflate_free(voidpf opaque, voidpf address)
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//----------------------------------------------------------------------------
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// Initialize decompression of the respective (HF or LF) FPGA stream
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// Initialize decompression of the respective (HF or LF) FPGA stream
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//----------------------------------------------------------------------------
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static bool reset_fpga_stream(int bitstream_version, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
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{
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uint8_t header[FPGA_BITSTREAM_FIXED_HEADER_SIZE];
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uncompressed_bytes_cnt = 0;
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// initialize z_stream structure for inflate:
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compressed_fpga_stream->next_in = &_binary_obj_fpga_all_bit_z_start;
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compressed_fpga_stream->avail_in = &_binary_obj_fpga_all_bit_z_end - &_binary_obj_fpga_all_bit_z_start;
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@ -247,7 +246,7 @@ static bool reset_fpga_stream(int bitstream_version, z_streamp compressed_fpga_s
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for (uint16_t i = 0; i < FPGA_BITSTREAM_FIXED_HEADER_SIZE; i++) {
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header[i] = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
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}
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// Check for a valid .bit file (starts with bitparse_fixed_header)
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if(memcmp(bitparse_fixed_header, header, FPGA_BITSTREAM_FIXED_HEADER_SIZE) == 0) {
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return true;
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@ -275,25 +274,25 @@ static void DownloadFPGA(int bitstream_version, int FpgaImageLen, z_streamp comp
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{
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//Dbprintf("DownloadFPGA(len: %d)", FpgaImageLen);
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int i=0;
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AT91C_BASE_PIOA->PIO_OER = GPIO_FPGA_ON;
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AT91C_BASE_PIOA->PIO_PER = GPIO_FPGA_ON;
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HIGH(GPIO_FPGA_ON); // ensure everything is powered on
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HIGH(GPIO_FPGA_ON); // ensure everything is powered on
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SpinDelay(50);
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LED_D_ON();
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// These pins are inputs
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AT91C_BASE_PIOA->PIO_ODR =
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GPIO_FPGA_NINIT |
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GPIO_FPGA_DONE;
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AT91C_BASE_PIOA->PIO_ODR =
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GPIO_FPGA_NINIT |
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GPIO_FPGA_DONE;
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// PIO controls the following pins
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AT91C_BASE_PIOA->PIO_PER =
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GPIO_FPGA_NINIT |
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GPIO_FPGA_DONE;
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AT91C_BASE_PIOA->PIO_PER =
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GPIO_FPGA_NINIT |
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GPIO_FPGA_DONE;
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// Enable pull-ups
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AT91C_BASE_PIOA->PIO_PPUER =
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GPIO_FPGA_NINIT |
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@ -305,8 +304,8 @@ static void DownloadFPGA(int bitstream_version, int FpgaImageLen, z_streamp comp
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LOW(GPIO_FPGA_DIN);
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// These pins are outputs
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AT91C_BASE_PIOA->PIO_OER =
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GPIO_FPGA_NPROGRAM |
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GPIO_FPGA_CCLK |
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GPIO_FPGA_NPROGRAM |
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GPIO_FPGA_CCLK |
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GPIO_FPGA_DIN;
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// enter FPGA configuration mode
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@ -335,7 +334,7 @@ static void DownloadFPGA(int bitstream_version, int FpgaImageLen, z_streamp comp
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}
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DownloadFPGA_byte(b);
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}
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// continue to clock FPGA until ready signal goes high
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i=100000;
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while ( (i--) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_DONE ) ) ) {
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@ -407,14 +406,14 @@ static int bitparse_find_section(int bitstream_version, char section_name, unsig
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//----------------------------------------------------------------------------
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// Check which FPGA image is currently loaded (if any). If necessary
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// Check which FPGA image is currently loaded (if any). If necessary
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// decompress and load the correct (HF or LF) image to the FPGA
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//----------------------------------------------------------------------------
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void FpgaDownloadAndGo(int bitstream_version)
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{
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z_stream compressed_fpga_stream;
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uint8_t output_buffer[OUTPUT_BUFFER_LEN] = {0x00};
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// check whether or not the bitstream is already loaded
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if (downloaded_bitstream == bitstream_version) {
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FpgaEnableTracing();
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@ -422,8 +421,8 @@ void FpgaDownloadAndGo(int bitstream_version)
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}
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// make sure that we have enough memory to decompress
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BigBuf_free(); BigBuf_Clear_ext(false);
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BigBuf_free(); BigBuf_Clear_ext(false);
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if (!reset_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer)) {
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return;
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}
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@ -435,13 +434,13 @@ void FpgaDownloadAndGo(int bitstream_version)
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}
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inflateEnd(&compressed_fpga_stream);
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// turn off antenna
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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// free eventually allocated BigBuf memory
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BigBuf_free(); BigBuf_Clear_ext(false);
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}
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BigBuf_free(); BigBuf_Clear_ext(false);
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}
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//-----------------------------------------------------------------------------
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@ -451,8 +450,8 @@ void FpgaDownloadAndGo(int bitstream_version)
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//-----------------------------------------------------------------------------
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void FpgaSendCommand(uint16_t cmd, uint16_t v) {
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SetupSpi(SPI_FPGA_MODE);
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while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TXEMPTY) == 0); // wait for the transfer to complete
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AT91C_BASE_SPI->SPI_TDR = AT91C_SPI_LASTXFER | cmd | v; // send the data
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AT91C_BASE_SPI->SPI_TDR = AT91C_SPI_LASTXFER | cmd | v; // write the data to be sent
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while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TXEMPTY) == 0); // wait for the transfer to complete
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}
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//-----------------------------------------------------------------------------
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@ -35,16 +35,17 @@ void SetAdcMuxFor(uint32_t whichGpio);
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#define FPGA_BITSTREAM_HF 2
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// Definitions for the FPGA commands.
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#define FPGA_CMD_MASK 0xF000
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// BOTH
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#define FPGA_CMD_SET_CONFREG (1<<12)
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#define FPGA_CMD_SET_CONFREG (1<<12)
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// LF
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#define FPGA_CMD_SET_DIVISOR (2<<12)
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#define FPGA_CMD_SET_EDGE_DETECT_THRESHOLD (3<<12)
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#define FPGA_CMD_SET_DIVISOR (2<<12)
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#define FPGA_CMD_SET_EDGE_DETECT_THRESHOLD (3<<12)
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// HF
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#define FPGA_CMD_TRACE_ENABLE (2<<12)
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#define FPGA_CMD_TRACE_ENABLE (2<<12)
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// Definitions for the FPGA configuration word.
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#define FPGA_MAJOR_MODE_MASK 0x01C0
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// LF
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#define FPGA_MAJOR_MODE_LF_ADC (0<<6)
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#define FPGA_MAJOR_MODE_LF_EDGE_DETECT (1<<6)
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@ -58,6 +59,7 @@ void SetAdcMuxFor(uint32_t whichGpio);
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// BOTH
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#define FPGA_MAJOR_MODE_OFF (7<<6)
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#define FPGA_MINOR_MODE_MASK 0x003F
|
||||
// Options for LF_ADC
|
||||
#define FPGA_LF_ADC_READER_FIELD (1<<0)
|
||||
|
||||
|
|
|
|||
|
|
@ -538,7 +538,7 @@ int doIClassSimulation(int simulationMode, uint8_t *reader_mac_buf) {
|
|||
if (modulated_response_size > 0) {
|
||||
uint32_t response_time = reader_eof_time + DELAY_ICLASS_VCD_TO_VICC_SIM;
|
||||
TransmitTo15693Reader(modulated_response, modulated_response_size, &response_time, 0, false);
|
||||
LogTrace_ISO15693(trace_data, trace_data_size, response_time*32, response_time*32 + modulated_response_size/2, NULL, false);
|
||||
LogTrace_ISO15693(trace_data, trace_data_size, response_time*32, response_time*32 + modulated_response_size*32*64, NULL, false);
|
||||
}
|
||||
|
||||
}
|
||||
|
|
@ -566,17 +566,11 @@ void SimulateIClass(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain
|
|||
|
||||
LED_A_ON();
|
||||
|
||||
Iso15693InitTag();
|
||||
|
||||
uint32_t simType = arg0;
|
||||
uint32_t numberOfCSNS = arg1;
|
||||
|
||||
// setup hardware for simulation:
|
||||
FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
|
||||
SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
|
||||
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_NO_MODULATION);
|
||||
LED_D_OFF();
|
||||
FpgaSetupSsc(FPGA_MAJOR_MODE_HF_SIMULATOR);
|
||||
StartCountSspClk();
|
||||
|
||||
// Enable and clear the trace
|
||||
set_tracing(true);
|
||||
clear_trace();
|
||||
|
|
@ -589,9 +583,8 @@ void SimulateIClass(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain
|
|||
doIClassSimulation(ICLASS_SIM_MODE_CSN, NULL);
|
||||
} else if (simType == ICLASS_SIM_MODE_CSN_DEFAULT) {
|
||||
//Default CSN
|
||||
uint8_t csn_crc[] = { 0x03, 0x1f, 0xec, 0x8a, 0xf7, 0xff, 0x12, 0xe0, 0x00, 0x00 };
|
||||
// Use the CSN from commandline
|
||||
memcpy(emulator, csn_crc, 8);
|
||||
uint8_t csn[] = {0x03, 0x1f, 0xec, 0x8a, 0xf7, 0xff, 0x12, 0xe0};
|
||||
memcpy(emulator, csn, 8);
|
||||
doIClassSimulation(ICLASS_SIM_MODE_CSN, NULL);
|
||||
} else if (simType == ICLASS_SIM_MODE_READER_ATTACK) {
|
||||
uint8_t mac_responses[USB_CMD_DATA_SIZE] = { 0 };
|
||||
|
|
@ -636,9 +629,7 @@ void SimulateIClass(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain
|
|||
static void ReaderTransmitIClass(uint8_t *frame, int len, uint32_t *start_time) {
|
||||
|
||||
CodeIso15693AsReader(frame, len);
|
||||
|
||||
TransmitTo15693Tag(ToSend, ToSendMax, start_time);
|
||||
|
||||
uint32_t end_time = *start_time + 32*(8*ToSendMax-4); // substract the 4 padding bits after EOF
|
||||
LogTrace_ISO15693(frame, len, *start_time*4, end_time*4, NULL, true);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -291,7 +291,6 @@ void TransmitTo15693Tag(const uint8_t *cmd, int len, uint32_t *start_time) {
|
|||
AT91C_BASE_SSC->SSC_THR = send_word;
|
||||
while (!(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY))) ;
|
||||
AT91C_BASE_SSC->SSC_THR = send_word;
|
||||
|
||||
data <<= 1;
|
||||
}
|
||||
WDT_HIT();
|
||||
|
|
@ -299,7 +298,6 @@ void TransmitTo15693Tag(const uint8_t *cmd, int len, uint32_t *start_time) {
|
|||
LED_B_OFF();
|
||||
|
||||
*start_time = *start_time + DELAY_ARM_TO_TAG;
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1357,20 +1355,23 @@ void SnoopIso15693(uint8_t jam_search_len, uint8_t *jam_search_string) {
|
|||
|
||||
|
||||
// Initialize the proxmark as iso15k reader
|
||||
void Iso15693InitReader() {
|
||||
void Iso15693InitReader(void) {
|
||||
FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
|
||||
|
||||
// Start from off (no field generated)
|
||||
LED_D_OFF();
|
||||
// switch field off and wait until tag resets
|
||||
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
|
||||
LED_D_OFF();
|
||||
SpinDelay(10);
|
||||
|
||||
SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
|
||||
FpgaSetupSsc(FPGA_MAJOR_MODE_HF_READER);
|
||||
|
||||
// Give the tags time to energize
|
||||
LED_D_ON();
|
||||
// switch field on
|
||||
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER);
|
||||
LED_D_ON();
|
||||
|
||||
// initialize SSC and select proper AD input
|
||||
FpgaSetupSsc(FPGA_MAJOR_MODE_HF_READER);
|
||||
SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
|
||||
|
||||
// give tags some time to energize
|
||||
SpinDelay(250);
|
||||
}
|
||||
|
||||
|
|
@ -1570,29 +1571,14 @@ void ReaderIso15693(uint32_t parameter) {
|
|||
|
||||
LED_A_ON();
|
||||
|
||||
Iso15693InitReader();
|
||||
|
||||
StartCountSspClk();
|
||||
set_tracing(true);
|
||||
|
||||
uint8_t TagUID[8] = {0x00};
|
||||
|
||||
FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
|
||||
|
||||
uint8_t answer[ISO15693_MAX_RESPONSE_LENGTH];
|
||||
|
||||
SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
|
||||
// Setup SSC
|
||||
FpgaSetupSsc(FPGA_MAJOR_MODE_HF_READER);
|
||||
|
||||
// Start from off (no field generated)
|
||||
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
|
||||
SpinDelay(200);
|
||||
|
||||
// Give the tags time to energize
|
||||
LED_D_ON();
|
||||
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER);
|
||||
SpinDelay(200);
|
||||
StartCountSspClk();
|
||||
|
||||
|
||||
// FIRST WE RUN AN INVENTORY TO GET THE TAG UID
|
||||
// THIS MEANS WE CAN PRE-BUILD REQUESTS TO SAVE CPU TIME
|
||||
|
||||
|
|
@ -1650,6 +1636,17 @@ void ReaderIso15693(uint32_t parameter) {
|
|||
}
|
||||
|
||||
|
||||
// Initialize the proxmark as iso15k tag
|
||||
void Iso15693InitTag(void) {
|
||||
FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
|
||||
SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
|
||||
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_NO_MODULATION);
|
||||
LED_D_OFF();
|
||||
FpgaSetupSsc(FPGA_MAJOR_MODE_HF_SIMULATOR);
|
||||
StartCountSspClk();
|
||||
}
|
||||
|
||||
|
||||
// Simulate an ISO15693 TAG.
|
||||
// For Inventory command: print command and send Inventory Response with given UID
|
||||
// TODO: interpret other reader commands and send appropriate response
|
||||
|
|
@ -1657,20 +1654,14 @@ void SimTagIso15693(uint32_t parameter, uint8_t *uid) {
|
|||
|
||||
LED_A_ON();
|
||||
|
||||
FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
|
||||
SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
|
||||
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_NO_MODULATION);
|
||||
FpgaSetupSsc(FPGA_MAJOR_MODE_HF_SIMULATOR);
|
||||
|
||||
StartCountSspClk();
|
||||
|
||||
uint8_t cmd[ISO15693_MAX_COMMAND_LENGTH];
|
||||
Iso15693InitTag();
|
||||
|
||||
// Build a suitable response to the reader INVENTORY command
|
||||
BuildInventoryResponse(uid);
|
||||
|
||||
// Listen to reader
|
||||
while (!BUTTON_PRESS()) {
|
||||
uint8_t cmd[ISO15693_MAX_COMMAND_LENGTH];
|
||||
uint32_t eof_time = 0, start_time = 0;
|
||||
int cmd_len = GetIso15693CommandFromReader(cmd, sizeof(cmd), &eof_time);
|
||||
|
||||
|
|
|
|||
|
|
@ -22,21 +22,22 @@
|
|||
#define DELAY_ISO15693_VCD_TO_VICC_READER 1056 // 1056/3,39MHz = 311.5us from end of command EOF to start of tag response
|
||||
#define DELAY_ISO15693_VICC_TO_VCD_READER 1024 // 1024/3.39MHz = 302.1us between end of tag response and next reader command
|
||||
|
||||
void Iso15693InitReader();
|
||||
void CodeIso15693AsReader(uint8_t *cmd, int n);
|
||||
void CodeIso15693AsTag(uint8_t *cmd, size_t len);
|
||||
void TransmitTo15693Reader(const uint8_t *cmd, size_t len, uint32_t *start_time, uint32_t slot_time, bool slow);
|
||||
int GetIso15693CommandFromReader(uint8_t *received, size_t max_len, uint32_t *eof_time);
|
||||
void TransmitTo15693Tag(const uint8_t *cmd, int len, uint32_t *start_time);
|
||||
int GetIso15693AnswerFromTag(uint8_t* response, uint16_t max_len, uint16_t timeout, uint32_t *eof_time);
|
||||
void SnoopIso15693(uint8_t jam_search_len, uint8_t *jam_search_string);
|
||||
void AcquireRawAdcSamplesIso15693(void);
|
||||
void ReaderIso15693(uint32_t parameter);
|
||||
void SimTagIso15693(uint32_t parameter, uint8_t *uid);
|
||||
void BruteforceIso15693Afi(uint32_t speed);
|
||||
void DirectTag15693Command(uint32_t datalen, uint32_t speed, uint32_t recv, uint8_t data[]);
|
||||
void SetTag15693Uid(uint8_t *uid);
|
||||
void SetDebugIso15693(uint32_t flag);
|
||||
bool LogTrace_ISO15693(const uint8_t *btBytes, uint16_t iLen, uint32_t timestamp_start, uint32_t timestamp_end, uint8_t *parity, bool readerToTag);
|
||||
extern void Iso15693InitReader(void);
|
||||
extern void Iso15693InitTag(void);
|
||||
extern void CodeIso15693AsReader(uint8_t *cmd, int n);
|
||||
extern void CodeIso15693AsTag(uint8_t *cmd, size_t len);
|
||||
extern void TransmitTo15693Reader(const uint8_t *cmd, size_t len, uint32_t *start_time, uint32_t slot_time, bool slow);
|
||||
extern int GetIso15693CommandFromReader(uint8_t *received, size_t max_len, uint32_t *eof_time);
|
||||
extern void TransmitTo15693Tag(const uint8_t *cmd, int len, uint32_t *start_time);
|
||||
extern int GetIso15693AnswerFromTag(uint8_t* response, uint16_t max_len, uint16_t timeout, uint32_t *eof_time);
|
||||
extern void SnoopIso15693(uint8_t jam_search_len, uint8_t *jam_search_string);
|
||||
extern void AcquireRawAdcSamplesIso15693(void);
|
||||
extern void ReaderIso15693(uint32_t parameter);
|
||||
extern void SimTagIso15693(uint32_t parameter, uint8_t *uid);
|
||||
extern void BruteforceIso15693Afi(uint32_t speed);
|
||||
extern void DirectTag15693Command(uint32_t datalen, uint32_t speed, uint32_t recv, uint8_t data[]);
|
||||
extern void SetTag15693Uid(uint8_t *uid);
|
||||
extern void SetDebugIso15693(uint32_t flag);
|
||||
extern bool LogTrace_ISO15693(const uint8_t *btBytes, uint16_t iLen, uint32_t timestamp_start, uint32_t timestamp_end, uint8_t *parity, bool readerToTag);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -137,8 +137,7 @@ void LED(int led, int ms)
|
|||
// not clicked, or held down (for ms || 1sec)
|
||||
// In general, don't use this function unless you expect a
|
||||
// double click, otherwise it will waste 500ms -- use BUTTON_HELD instead
|
||||
int BUTTON_CLICKED(int ms)
|
||||
{
|
||||
int BUTTON_CLICKED(int ms) {
|
||||
// Up to 500ms in between clicks to mean a double click
|
||||
int ticks = (48000 * (ms ? ms : 1000)) >> 10;
|
||||
|
||||
|
|
@ -200,8 +199,7 @@ int BUTTON_CLICKED(int ms)
|
|||
}
|
||||
|
||||
// Determine if a button is held down
|
||||
int BUTTON_HELD(int ms)
|
||||
{
|
||||
int BUTTON_HELD(int ms) {
|
||||
// If button is held for one second
|
||||
int ticks = (48000 * (ms ? ms : 1000)) >> 10;
|
||||
|
||||
|
|
@ -218,8 +216,7 @@ int BUTTON_HELD(int ms)
|
|||
|
||||
uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
|
||||
|
||||
for(;;)
|
||||
{
|
||||
for(;;) {
|
||||
uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
|
||||
|
||||
// As soon as our button let go, we didn't hold long enough
|
||||
|
|
@ -227,8 +224,7 @@ int BUTTON_HELD(int ms)
|
|||
return BUTTON_SINGLE_CLICK;
|
||||
|
||||
// Have we waited the full second?
|
||||
else
|
||||
if (now == (uint16_t)(start + ticks))
|
||||
else if (now == (uint16_t)(start + ticks))
|
||||
return BUTTON_HOLD;
|
||||
|
||||
WDT_HIT();
|
||||
|
|
@ -240,8 +236,7 @@ int BUTTON_HELD(int ms)
|
|||
|
||||
// attempt at high resolution microsecond timer
|
||||
// beware: timer counts in 21.3uS increments (1024/48Mhz)
|
||||
void SpinDelayUs(int us)
|
||||
{
|
||||
void SpinDelayUs(int us) {
|
||||
int ticks = (48*us) >> 10;
|
||||
|
||||
// Borrow a PWM unit for my real-time clock
|
||||
|
|
@ -262,8 +257,7 @@ void SpinDelayUs(int us)
|
|||
}
|
||||
}
|
||||
|
||||
void SpinDelay(int ms)
|
||||
{
|
||||
void SpinDelay(int ms) {
|
||||
// convert to uS and call microsecond delay function
|
||||
SpinDelayUs(ms*1000);
|
||||
}
|
||||
|
|
@ -314,8 +308,7 @@ void FormatVersionInformation(char *dst, int len, const char *prefix, void *vers
|
|||
// ti = GetTickCount() - ti;
|
||||
// Dbprintf("timer(1s): %d t=%d", ti, GetTickCount());
|
||||
|
||||
void StartTickCount()
|
||||
{
|
||||
void StartTickCount() {
|
||||
// This timer is based on the slow clock. The slow clock frequency is between 22kHz and 40kHz.
|
||||
// We can determine the actual slow clock frequency by looking at the Main Clock Frequency Register.
|
||||
uint16_t mainf = AT91C_BASE_PMC->PMC_MCFR & 0xffff; // = 16 * main clock frequency (16MHz) / slow clock frequency
|
||||
|
|
@ -328,7 +321,7 @@ void StartTickCount()
|
|||
/*
|
||||
* Get the current count.
|
||||
*/
|
||||
uint32_t RAMFUNC GetTickCount(){
|
||||
uint32_t RAMFUNC GetTickCount(void) {
|
||||
return AT91C_BASE_RTTC->RTTC_RTVR;// was * 2;
|
||||
}
|
||||
|
||||
|
|
@ -336,8 +329,7 @@ uint32_t RAMFUNC GetTickCount(){
|
|||
// -------------------------------------------------------------------------
|
||||
// microseconds timer
|
||||
// -------------------------------------------------------------------------
|
||||
void StartCountUS()
|
||||
{
|
||||
void StartCountUS(void) {
|
||||
AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);
|
||||
// AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC1XC1S_TIOA0;
|
||||
AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
|
||||
|
|
@ -359,14 +351,14 @@ void StartCountUS()
|
|||
}
|
||||
|
||||
|
||||
uint32_t RAMFUNC GetCountUS(){
|
||||
uint32_t RAMFUNC GetCountUS(void) {
|
||||
return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV * 2) / 3); //was /15) * 10);
|
||||
}
|
||||
|
||||
|
||||
static uint32_t GlobalUsCounter = 0;
|
||||
|
||||
uint32_t RAMFUNC GetDeltaCountUS(){
|
||||
uint32_t RAMFUNC GetDeltaCountUS(void) {
|
||||
uint32_t g_cnt = GetCountUS();
|
||||
uint32_t g_res = g_cnt - GlobalUsCounter;
|
||||
GlobalUsCounter = g_cnt;
|
||||
|
|
@ -377,8 +369,7 @@ uint32_t RAMFUNC GetDeltaCountUS(){
|
|||
// -------------------------------------------------------------------------
|
||||
// Timer for iso14443 commands. Uses ssp_clk from FPGA
|
||||
// -------------------------------------------------------------------------
|
||||
void StartCountSspClk()
|
||||
{
|
||||
void StartCountSspClk(void) {
|
||||
AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1) | (1 << AT91C_ID_TC2); // Enable Clock to all timers
|
||||
AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1 // XC0 Clock = TIOA1
|
||||
| AT91C_TCB_TC1XC1S_NONE // XC1 Clock = none
|
||||
|
|
@ -395,7 +386,7 @@ void StartCountSspClk()
|
|||
| AT91C_TC_WAVE // Waveform Mode
|
||||
| AT91C_TC_AEEVT_SET // Set TIOA1 on external event
|
||||
| AT91C_TC_ACPC_CLEAR; // Clear TIOA1 on RC Compare
|
||||
AT91C_BASE_TC1->TC_RC = 0x02; // RC Compare value = 0x02
|
||||
AT91C_BASE_TC1->TC_RC = 1; // RC Compare value = 1; pulse width to TC0
|
||||
|
||||
// use TC0 to count TIOA1 pulses
|
||||
AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // disable TC0
|
||||
|
|
@ -425,7 +416,7 @@ void StartCountSspClk()
|
|||
while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high; 1st ssp_clk after start of frame
|
||||
while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK); // wait for ssp_clk to go low;
|
||||
while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high; 2nd ssp_clk after start of frame
|
||||
if ((AT91C_BASE_SSC->SSC_RFMR & SSC_FRAME_MODE_BITS_IN_WORD(32)) == SSC_FRAME_MODE_BITS_IN_WORD(16)) {
|
||||
if ((AT91C_BASE_SSC->SSC_RFMR & SSC_FRAME_MODE_BITS_IN_WORD(32)) == SSC_FRAME_MODE_BITS_IN_WORD(16)) { // 16bit frame
|
||||
while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK); // wait for ssp_clk to go low;
|
||||
while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high; 3rd ssp_clk after start of frame
|
||||
while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK); // wait for ssp_clk to go low;
|
||||
|
|
@ -439,8 +430,8 @@ void StartCountSspClk()
|
|||
AT91C_BASE_TCB->TCB_BCR = 1; // assert Sync (set all timers to 0 on next active clock edge)
|
||||
// at the next (3rd/7th) ssp_clk rising edge, TC1 will be reset (and not generate a clock signal to TC0)
|
||||
// at the next (4th/8th) ssp_clk rising edge, TC0 (the low word of our counter) will be reset. From now on,
|
||||
// whenever the last three bits of our counter go 0, we can be sure to be in the middle of a frame transfer.
|
||||
// (just started with the transfer of the 3rd Bit).
|
||||
// whenever the last three/four bits of our counter go 0, we can be sure to be in the middle of a frame transfer.
|
||||
|
||||
// The high word of the counter (TC2) will not reset until the low word (TC0) overflows. Therefore need to wait quite some time before
|
||||
// we can use the counter.
|
||||
while (AT91C_BASE_TC0->TC_CV < 0xFFFF);
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
#
|
||||
#BEGIN
|
||||
APP_CFLAGS += -DWITH_ISO14443a_StandAlone \
|
||||
-DWITH_LF\
|
||||
-DWITH_LF \
|
||||
-DWITH_ISO15693 \
|
||||
-DWITH_ISO14443a \
|
||||
-DWITH_ISO14443b \
|
||||
|
|
|
|||
BIN
fpga/fpga_hf.bit
BIN
fpga/fpga_hf.bit
Binary file not shown.
|
|
@ -30,16 +30,16 @@ reg after_hysteresis, after_hysteresis_prev, after_hysteresis_prev_prev;
|
|||
reg [11:0] has_been_low_for;
|
||||
always @(negedge adc_clk)
|
||||
begin
|
||||
if(& adc_d[7:0]) after_hysteresis <= 1'b1;
|
||||
else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;
|
||||
if (& adc_d[7:0]) after_hysteresis <= 1'b1;
|
||||
else if (~(| adc_d[7:0])) after_hysteresis <= 1'b0;
|
||||
|
||||
if(after_hysteresis)
|
||||
if (after_hysteresis)
|
||||
begin
|
||||
has_been_low_for <= 7'b0;
|
||||
has_been_low_for <= 12'd0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if(has_been_low_for == 12'd4095)
|
||||
if (has_been_low_for == 12'd4095)
|
||||
begin
|
||||
has_been_low_for <= 12'd0;
|
||||
after_hysteresis <= 1'b1;
|
||||
|
|
@ -235,6 +235,16 @@ end
|
|||
|
||||
|
||||
// ssp clock and frame signal for communication to and from ARM
|
||||
// _____ _____ _____ _
|
||||
// ssp_clk | |_____| |_____| |_____|
|
||||
// _____
|
||||
// ssp_frame ___| |____________________________
|
||||
// ___________ ___________ ___________ _
|
||||
// ssp_d_in X___________X___________X___________X_
|
||||
//
|
||||
// corr_i_cnt 0 1 2 3 4 5 6 7 8 9 10 11 12 ...
|
||||
//
|
||||
|
||||
reg ssp_clk;
|
||||
reg ssp_frame;
|
||||
|
||||
|
|
@ -249,7 +259,7 @@ begin
|
|||
// (send one frame with 16 Bits)
|
||||
if (corr_i_cnt == 6'd1)
|
||||
ssp_frame <= 1'b1;
|
||||
if (corr_i_cnt == 6'd5)
|
||||
if (corr_i_cnt == 6'd3)
|
||||
ssp_frame <= 1'b0;
|
||||
end
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue