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https://github.com/Proxmark/proxmark3.git
synced 2025-07-16 02:03:00 -07:00
Implemented new FPGA mode for iclass tag simulation. Reduces arm-side size of transfer/memory by a factor of 8. Makes for easier arm-side encoding of messages, for when we start needing to do that on the fly instead of using precalculated messages
This commit is contained in:
Martin Holst Swende
parent
55eaed8f2a
commit
645c960f61
4 changed files with 118 additions and 59 deletions
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@ -134,6 +134,8 @@ void SetAdcMuxFor(uint32_t whichGpio);
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#define FPGA_HF_SIMULATOR_MODULATE_BPSK (1<<0)
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#define FPGA_HF_SIMULATOR_MODULATE_212K (2<<0)
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#define FPGA_HF_SIMULATOR_MODULATE_424K (4<<0)
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#define FPGA_HF_SIMULATOR_MODULATE_424K_8BIT 0x5//101
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// Options for ISO14443A
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#define FPGA_HF_ISO14443A_SNIFFER (0<<0)
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#define FPGA_HF_ISO14443A_TAGSIM_LISTEN (1<<0)
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136
armsrc/iclass.c
136
armsrc/iclass.c
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@ -857,57 +857,93 @@ static int GetIClassCommandFromReader(uint8_t *received, int *len, int maxLen)
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}
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}
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static uint8_t encode4Bits(const uint8_t b)
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{
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uint8_t c = b & 0xF;
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// OTA, the least significant bits first
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// The columns are
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// 1 - Bit value to send
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// 2 - Reversed (big-endian)
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// 3 - Encoded
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// 4 - Hex values
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switch(c){
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// 1 2 3 4
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case 15: return 0x55; // 1111 -> 1111 -> 01010101 -> 0x55
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case 14: return 0x95; // 1110 -> 0111 -> 10010101 -> 0x95
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case 13: return 0x65; // 1101 -> 1011 -> 01100101 -> 0x65
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case 12: return 0xa5; // 1100 -> 0011 -> 10100101 -> 0xa5
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case 11: return 0x59; // 1011 -> 1101 -> 01011001 -> 0x59
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case 10: return 0x99; // 1010 -> 0101 -> 10011001 -> 0x99
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case 9: return 0x69; // 1001 -> 1001 -> 01101001 -> 0x69
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case 8: return 0xa9; // 1000 -> 0001 -> 10101001 -> 0xa9
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case 7: return 0x56; // 0111 -> 1110 -> 01010110 -> 0x56
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case 6: return 0x96; // 0110 -> 0110 -> 10010110 -> 0x96
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case 5: return 0x66; // 0101 -> 1010 -> 01100110 -> 0x66
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case 4: return 0xa6; // 0100 -> 0010 -> 10100110 -> 0xa6
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case 3: return 0x5a; // 0011 -> 1100 -> 01011010 -> 0x5a
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case 2: return 0x9a; // 0010 -> 0100 -> 10011010 -> 0x9a
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case 1: return 0x6a; // 0001 -> 1000 -> 01101010 -> 0x6a
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default: return 0xaa; // 0000 -> 0000 -> 10101010 -> 0xaa
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}
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}
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//-----------------------------------------------------------------------------
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// Prepare tag messages
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//-----------------------------------------------------------------------------
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static void CodeIClassTagAnswer(const uint8_t *cmd, int len)
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{
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//So far a dummy implementation, not used
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//int lastProxToAirDuration =0;
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/*
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* SOF comprises 3 parts;
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* * An unmodulated time of 56.64 us
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* * 24 pulses of 423.75 KHz (fc/32)
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* * A logic 1, which starts with an unmodulated time of 18.88us
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* followed by 8 pulses of 423.75kHz (fc/32)
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*
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*
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* EOF comprises 3 parts:
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* - A logic 0 (which starts with 8 pulses of fc/32 followed by an unmodulated
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* time of 18.88us.
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* - 24 pulses of fc/32
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* - An unmodulated time of 56.64 us
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*
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*
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* A logic 0 starts with 8 pulses of fc/32
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* followed by an unmodulated time of 256/fc (~18,88us).
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*
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* A logic 0 starts with unmodulated time of 256/fc (~18,88us) followed by
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* 8 pulses of fc/32 (also 18.88us)
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*
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* The mode FPGA_HF_SIMULATOR_MODULATE_424K_8BIT which we use to simulate tag,
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* works like this.
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* - A 1-bit input to the FPGA becomes 8 pulses on 423.5kHz (fc/32) (18.88us).
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* - A 0-bit inptu to the FPGA becomes an unmodulated time of 18.88us
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*
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* In thist mode the SOF can be written as 00011101 = 0x1D
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* The EOF can be written as 10111000 = 0xb8
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* A logic 1 is 01
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* A logic 0 is 10
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*
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* */
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int i;
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ToSendReset();
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// Send SOF
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ToSend[++ToSendMax] = 0x00;
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ToSend[++ToSendMax] = 0x00;
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ToSend[++ToSendMax] = 0x00;
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ToSend[++ToSendMax] = 0xff;//Proxtoair duration starts here
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ToSend[++ToSendMax] = 0xff;
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ToSend[++ToSendMax] = 0xff;
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ToSend[++ToSendMax] = 0x00;
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ToSend[++ToSendMax] = 0xff;
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ToSend[++ToSendMax] = 0x1D;
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for(i = 0; i < len; i++) {
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int j;
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uint8_t b = cmd[i];
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// Data bits
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for(j = 0; j < 8; j++) {
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if(b & 1) {
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ToSend[++ToSendMax] = 0x00;
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ToSend[++ToSendMax] = 0xff;
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} else {
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ToSend[++ToSendMax] = 0xff;
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ToSend[++ToSendMax] = 0x00;
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}
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b >>= 1;
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}
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ToSend[++ToSendMax] = encode4Bits(b & 0xF); //Least significant half
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ToSend[++ToSendMax] = encode4Bits((b >>4) & 0xF);//Most significant half
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}
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// Send EOF
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ToSend[++ToSendMax] = 0xff;
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ToSend[++ToSendMax] = 0x00;
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ToSend[++ToSendMax] = 0xff;
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ToSend[++ToSendMax] = 0xff;
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ToSend[++ToSendMax] = 0xff;
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ToSend[++ToSendMax] = 0x00;
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ToSend[++ToSendMax] = 0x00;
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ToSend[++ToSendMax] = 0x00;
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ToSend[++ToSendMax] = 0xB8;
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//lastProxToAirDuration = 8*ToSendMax - 3*8 - 3*8;//Not counting zeroes in the beginning or end
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// Convert from last byte pos to length
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ToSendMax++;
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}
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@ -920,18 +956,9 @@ static void CodeIClassTagSOF()
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ToSendReset();
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// Send SOF
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ToSend[++ToSendMax] = 0x00;
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ToSend[++ToSendMax] = 0x00;
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ToSend[++ToSendMax] = 0x00;
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ToSend[++ToSendMax] = 0xff;
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ToSend[++ToSendMax] = 0xff;
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ToSend[++ToSendMax] = 0xff;
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ToSend[++ToSendMax] = 0x00;
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ToSend[++ToSendMax] = 0xff;
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ToSend[++ToSendMax] = 0x1D;
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// lastProxToAirDuration = 8*ToSendMax - 3*8;//Not counting zeroes in the beginning
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// Convert from last byte pos to length
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ToSendMax++;
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}
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@ -984,6 +1011,7 @@ void SimulateIClass(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain
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memcpy(csn_crc, datain+(i*8), 8);
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if(doIClassSimulation(csn_crc,1,mac_responses+i*8))
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{
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cmd_send(CMD_ACK,CMD_SIMULATE_TAG_ICLASS,i,0,mac_responses,i*8);
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return; // Button pressed
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}
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}
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@ -1036,23 +1064,23 @@ int doIClassSimulation(uint8_t csn[], int breakAfterMacReceived, uint8_t *reader
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int trace_data_size = 0;
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//uint8_t sof = 0x0f;
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// Respond SOF -- takes 8 bytes
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// Respond SOF -- takes 1 bytes
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uint8_t *resp1 = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET);
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int resp1Len;
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// Anticollision CSN (rotated CSN)
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// 176: Takes 16 bytes for SOF/EOF and 10 * 16 = 160 bytes (2 bytes/bit)
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uint8_t *resp2 = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET + 10);
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// 22: Takes 2 bytes for SOF/EOF and 10 * 2 = 20 bytes (2 bytes/byte)
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uint8_t *resp2 = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET + 2);
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int resp2Len;
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// CSN
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// 176: Takes 16 bytes for SOF/EOF and 10 * 16 = 160 bytes (2 bytes/bit)
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uint8_t *resp3 = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET + 190);
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// 22: Takes 2 bytes for SOF/EOF and 10 * 2 = 20 bytes (2 bytes/byte)
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uint8_t *resp3 = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET + 30);
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int resp3Len;
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// e-Purse
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// 144: Takes 16 bytes for SOF/EOF and 8 * 16 = 128 bytes (2 bytes/bit)
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uint8_t *resp4 = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET + 370);
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// 18: Takes 2 bytes for SOF/EOF and 8 * 2 = 16 bytes (2 bytes/byte)
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uint8_t *resp4 = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET + 60);
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int resp4Len;
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// + 1720..
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@ -1195,7 +1223,7 @@ int doIClassSimulation(uint8_t csn[], int breakAfterMacReceived, uint8_t *reader
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A legit tag has about 380us.
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**/
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if(modulated_response_size > 0) {
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SendIClassAnswer(modulated_response, modulated_response_size, timeout);
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SendIClassAnswer(modulated_response, modulated_response_size, 1);
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t2r_time = GetCountSspClk();
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}
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@ -1232,7 +1260,8 @@ static int SendIClassAnswer(uint8_t *resp, int respLen, int delay)
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int i = 0, d=0;//, u = 0, d = 0;
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uint8_t b = 0;
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR|FPGA_HF_SIMULATOR_MODULATE_424K);
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//FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR|FPGA_HF_SIMULATOR_MODULATE_424K);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR|FPGA_HF_SIMULATOR_MODULATE_424K_8BIT);
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AT91C_BASE_SSC->SSC_THR = 0x00;
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FpgaSetupSsc();
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@ -1256,7 +1285,8 @@ static int SendIClassAnswer(uint8_t *resp, int respLen, int delay)
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AT91C_BASE_SSC->SSC_THR = b;
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}
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if (i > respLen +4) break;
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// if (i > respLen +4) break;
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if (i > respLen +1) break;
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}
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return 0;
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BIN
fpga/fpga_hf.bit
BIN
fpga/fpga_hf.bit
Binary file not shown.
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@ -50,12 +50,38 @@ begin
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else if(~(| adc_d[7:5])) after_hysteresis = 1'b0;
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end
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// Divide 13.56 MHz by 32 to produce the SSP_CLK
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// The register is bigger to allow higher division factors of up to /128
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reg [6:0] ssp_clk_divider;
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reg [10:0] ssp_clk_divider;
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always @(posedge adc_clk)
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ssp_clk_divider <= (ssp_clk_divider + 1);
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assign ssp_clk = ssp_clk_divider[4];
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reg ssp_clk;
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reg ssp_frame;
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always @(negedge adc_clk)
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begin
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//If we're in 101, we only need a new bit every 8th carrier bit (53Hz). Otherwise, get next bit at 424Khz
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if(mod_type == 3'b101)
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begin
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if(ssp_clk_divider[7:0] == 8'b00000000)
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ssp_clk <= 1'b0;
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if(ssp_clk_divider[7:0] == 8'b10000000)
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ssp_clk <= 1'b1;
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end
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else
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begin
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if(ssp_clk_divider[4:0] == 5'd0)//[4:0] == 5'b00000)
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ssp_clk <= 1'b1;
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if(ssp_clk_divider[4:0] == 5'd16) //[4:0] == 5'b10000)
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ssp_clk <= 1'b0;
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end
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end
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//assign ssp_clk = ssp_clk_divider[4];
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// Divide SSP_CLK by 8 to produce the byte framing signal; the phase of
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// this is arbitrary, because it's just a bitstream.
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@ -69,12 +95,13 @@ reg [2:0] ssp_frame_divider_from_arm;
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always @(negedge ssp_clk)
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ssp_frame_divider_from_arm <= (ssp_frame_divider_from_arm + 1);
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reg ssp_frame;
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always @(ssp_frame_divider_to_arm or ssp_frame_divider_from_arm or mod_type)
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if(mod_type == 3'b000) // not modulating, so listening, to ARM
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ssp_frame = (ssp_frame_divider_to_arm == 3'b000);
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else
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ssp_frame = (ssp_frame_divider_from_arm == 3'b000);
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ssp_frame = (ssp_frame_divider_from_arm == 3'b000);
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// Synchronize up the after-hysteresis signal, to produce DIN.
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reg ssp_din;
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@ -90,7 +117,7 @@ always @(mod_type or ssp_clk or ssp_dout)
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modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK
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else if(mod_type == 3'b010)
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modulating_carrier <= ssp_dout & ssp_clk_divider[5]; // switch 212kHz subcarrier on/off
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else if(mod_type == 3'b100)
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else if(mod_type == 3'b100 || mod_type == 3'b101)
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modulating_carrier <= ssp_dout & ssp_clk_divider[4]; // switch 424kHz modulation on/off
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else
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modulating_carrier <= 1'b0; // yet unused
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@ -106,7 +133,7 @@ assign pwr_oe4 = modulating_carrier;
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// This one is always on, so that we can watch the carrier.
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assign pwr_oe3 = 1'b0;
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assign dbg = after_hysteresis;
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assign dbg = modulating_carrier;
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//reg dbg;
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//always @(ssp_dout)
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// dbg <= ssp_dout;
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