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FPGA changes (#803)
* merge hf_rx_xcorr and hf_tx modes into one module with common ssp_clk and ssp_frame * get rid of most of the warnings when compiling the HF verilog sources * refactoring the constants in Verilog sources
This commit is contained in:
pwpiwi
GitHub
parent
ca8a3478d9
commit
5ea2a24839
17 changed files with 426 additions and 498 deletions
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@ -1,11 +1,11 @@
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include ../common/Makefile.common
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include ../common/Makefile.common # for $(DETECTED_OS)
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all: fpga_lf.bit fpga_hf.bit
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clean:
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$(DELETE) *.bgn *.drc *.ncd *.ngd *_par.xrpt *-placed.* *-placed_pad.* *_usage.xml xst_hf.srp xst_lf.srp
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$(DELETE) *.map *.ngc *.xrpt *.pcf *.rbt *_auto_* *.bld *.mrp *.ngm *.unroutes *_summary.xml netlist.lst xst
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fpga_hf.ngc: fpga_hf.v fpga.ucf xst_hf.scr util.v hi_simulate.v hi_read_tx.v hi_read_rx_xcorr.v hi_iso14443a.v hi_sniffer.v hi_get_trace.v
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fpga_hf.ngc: fpga_hf.v fpga.ucf xst_hf.scr util.v hi_simulate.v hi_reader.v hi_iso14443a.v hi_sniffer.v hi_get_trace.v
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$(DELETE) $@
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$(XILINX_TOOLS_PREFIX)xst -ifn xst_hf.scr
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@ -1,38 +1,38 @@
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# See the schematic for the pin assignment.
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NET "adc_d<0>" LOC = "P62" ;
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NET "adc_d<1>" LOC = "P60" ;
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NET "adc_d<2>" LOC = "P58" ;
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NET "adc_d<3>" LOC = "P57" ;
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NET "adc_d<4>" LOC = "P56" ;
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NET "adc_d<5>" LOC = "P55" ;
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NET "adc_d<6>" LOC = "P54" ;
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NET "adc_d<7>" LOC = "P53" ;
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#NET "cross_hi" LOC = "P88" ;
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#NET "miso" LOC = "P40" ;
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NET "adc_d<0>" LOC = "P62" ;
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NET "adc_d<1>" LOC = "P60" ;
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NET "adc_d<2>" LOC = "P58" ;
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NET "adc_d<3>" LOC = "P57" ;
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NET "adc_d<4>" LOC = "P56" ;
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NET "adc_d<5>" LOC = "P55" ;
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NET "adc_d<6>" LOC = "P54" ;
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NET "adc_d<7>" LOC = "P53" ;
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NET "cross_hi" LOC = "P88" ;
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#NET "miso" LOC = "P40" ;
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#PACE: Start of Constraints generated by PACE
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#PACE: Start of PACE I/O Pin Assignments
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NET "adc_clk" LOC = "P46" ;
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NET "adc_noe" LOC = "P47" ;
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NET "ck_1356meg" LOC = "P91" ;
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NET "ck_1356megb" LOC = "P93" ;
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NET "cross_lo" LOC = "P87" ;
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NET "dbg" LOC = "P22" ;
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NET "mosi" LOC = "P43" ;
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NET "ncs" LOC = "P44" ;
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NET "pck0" LOC = "P36" ;
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NET "pwr_hi" LOC = "P80" ;
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NET "pwr_lo" LOC = "P81" ;
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NET "pwr_oe1" LOC = "P82" ;
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NET "pwr_oe2" LOC = "P83" ;
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NET "pwr_oe3" LOC = "P84" ;
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NET "pwr_oe4" LOC = "P86" ;
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NET "spck" LOC = "P39" ;
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NET "ssp_clk" LOC = "P71" ;
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NET "ssp_din" LOC = "P32" ;
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NET "ssp_dout" LOC = "P34" ;
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NET "ssp_frame" LOC = "P31" ;
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NET "adc_clk" LOC = "P46" ;
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NET "adc_noe" LOC = "P47" ;
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NET "ck_1356meg" LOC = "P91" ;
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NET "ck_1356megb" LOC = "P93" ;
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NET "cross_lo" LOC = "P87" ;
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NET "dbg" LOC = "P22" ;
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NET "mosi" LOC = "P43" ;
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NET "ncs" LOC = "P44" ;
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NET "pck0" LOC = "P36" ;
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NET "pwr_hi" LOC = "P80" ;
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NET "pwr_lo" LOC = "P81" ;
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NET "pwr_oe1" LOC = "P82" ;
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NET "pwr_oe2" LOC = "P83" ;
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NET "pwr_oe3" LOC = "P84" ;
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NET "pwr_oe4" LOC = "P86" ;
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NET "spck" LOC = "P39" ;
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NET "ssp_clk" LOC = "P71" ;
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NET "ssp_din" LOC = "P32" ;
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NET "ssp_dout" LOC = "P34" ;
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NET "ssp_frame" LOC = "P31" ;
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#PACE: Start of PACE Area Constraints
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BIN
fpga/fpga_hf.bit
BIN
fpga/fpga_hf.bit
Binary file not shown.
161
fpga/fpga_hf.v
161
fpga/fpga_hf.v
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@ -13,8 +13,47 @@
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// iZsh <izsh at fail0verflow.com>, June 2014
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//-----------------------------------------------------------------------------
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`include "hi_read_tx.v"
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`include "hi_read_rx_xcorr.v"
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// Defining modes and options. This must be aligned to the definitions in fpgaloader.h
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// Note: the definitions here are without shifts
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// Major modes:
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`define FPGA_MAJOR_MODE_LF_ADC 0
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`define FPGA_MAJOR_MODE_LF_EDGE_DETECT 1
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`define FPGA_MAJOR_MODE_LF_PASSTHRU 2
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`define FPGA_MAJOR_MODE_HF_READER 0
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`define FPGA_MAJOR_MODE_HF_SIMULATOR 1
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`define FPGA_MAJOR_MODE_HF_ISO14443A 2
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`define FPGA_MAJOR_MODE_HF_SNOOP 3
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`define FPGA_MAJOR_MODE_HF_GET_TRACE 4
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`define FPGA_MAJOR_MODE_OFF 7
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// Options for the generic HF reader
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`define FPGA_HF_READER_MODE_RECEIVE_IQ 0
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`define FPGA_HF_READER_MODE_RECEIVE_AMPLITUDE 1
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`define FPGA_HF_READER_MODE_RECEIVE_PHASE 2
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`define FPGA_HF_READER_MODE_SEND_FULL_MOD 3
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`define FPGA_HF_READER_MODE_SEND_SHALLOW_MOD 4
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`define FPGA_HF_READER_MODE_SNIFF_IQ 5
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`define FPGA_HF_READER_MODE_SNIFF_AMPLITUDE 6
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`define FPGA_HF_READER_MODE_SNIFF_PHASE 7
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`define FPGA_HF_READER_SUBCARRIER_848_KHZ 0
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`define FPGA_HF_READER_SUBCARRIER_424_KHZ 1
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`define FPGA_HF_READER_SUBCARRIER_212_KHZ 2
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// Options for the HF simulated tag, how to modulate
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`define FPGA_HF_SIMULATOR_NO_MODULATION 0
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`define FPGA_HF_SIMULATOR_MODULATE_BPSK 1
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`define FPGA_HF_SIMULATOR_MODULATE_212K 2
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`define FPGA_HF_SIMULATOR_MODULATE_424K 4
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`define FPGA_HF_SIMULATOR_MODULATE_424K_8BIT 5
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// Options for ISO14443A
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`define FPGA_HF_ISO14443A_SNIFFER 0
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`define FPGA_HF_ISO14443A_TAGSIM_LISTEN 1
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`define FPGA_HF_ISO14443A_TAGSIM_MOD 2
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`define FPGA_HF_ISO14443A_READER_LISTEN 3
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`define FPGA_HF_ISO14443A_READER_MOD 4
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`include "hi_reader.v"
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`include "hi_simulate.v"
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`include "hi_iso14443a.v"
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`include "hi_sniffer.v"
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@ -49,8 +88,8 @@ reg trace_enable;
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always @(posedge ncs)
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begin
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case(shift_reg[15:12])
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4'b0001: conf_word <= shift_reg[7:0]; // FPGA_CMD_SET_CONFREG
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4'b0010: trace_enable <= shift_reg[0]; // FPGA_CMD_TRACE_ENABLE
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4'b0001: conf_word <= shift_reg[7:0]; // FPGA_CMD_SET_CONFREG
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4'b0010: trace_enable <= shift_reg[0]; // FPGA_CMD_TRACE_ENABLE
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endcase
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end
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@ -63,26 +102,12 @@ begin
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end
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end
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wire [2:0] major_mode;
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assign major_mode = conf_word[7:5];
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// select module (outputs) based on major mode
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wire [2:0] major_mode = conf_word[7:5];
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// For the high-frequency transmit configuration: modulation depth, either
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// 100% (just quite driving antenna, steady LOW), or shallower (tri-state
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// some fraction of the buffers)
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wire hi_read_tx_shallow_modulation = conf_word[0];
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// For the high-frequency receive correlator: frequency against which to
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// correlate.
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wire hi_read_rx_xcorr_848 = conf_word[0];
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// and whether to drive the coil (reader) or just short it (snooper)
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wire hi_read_rx_xcorr_snoop = conf_word[1];
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// divide subcarrier frequency by 4
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wire hi_read_rx_xcorr_quarter = conf_word[2];
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// send amplitude only instead of ci/cq pair
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wire hi_read_rx_xcorr_amplitude = conf_word[3];
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// For the high-frequency simulated tag: what kind of modulation to use.
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wire [2:0] hi_simulate_mod_type = conf_word[2:0];
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// configuring the HF reader
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wire [1:0] subcarrier_frequency = conf_word[4:3];
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wire [2:0] minor_mode = conf_word[2:0];
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//-----------------------------------------------------------------------------
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// And then we instantiate the modules corresponding to each of the FPGA's
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@ -90,85 +115,71 @@ wire [2:0] hi_simulate_mod_type = conf_word[2:0];
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// the output pins.
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//-----------------------------------------------------------------------------
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hi_read_tx ht(
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pck0, ck_1356meg, ck_1356megb,
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ht_pwr_lo, ht_pwr_hi, ht_pwr_oe1, ht_pwr_oe2, ht_pwr_oe3, ht_pwr_oe4,
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adc_d, ht_adc_clk,
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ht_ssp_frame, ht_ssp_din, ssp_dout, ht_ssp_clk,
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cross_hi, cross_lo,
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ht_dbg,
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hi_read_tx_shallow_modulation
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);
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hi_read_rx_xcorr hrxc(
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pck0, ck_1356meg, ck_1356megb,
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hrxc_pwr_lo, hrxc_pwr_hi, hrxc_pwr_oe1, hrxc_pwr_oe2, hrxc_pwr_oe3, hrxc_pwr_oe4,
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adc_d, hrxc_adc_clk,
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hrxc_ssp_frame, hrxc_ssp_din, ssp_dout, hrxc_ssp_clk,
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cross_hi, cross_lo,
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hrxc_dbg,
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hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop, hi_read_rx_xcorr_quarter, hi_read_rx_xcorr_amplitude
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hi_reader hr(
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ck_1356megb,
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hr_pwr_lo, hr_pwr_hi, hr_pwr_oe1, hr_pwr_oe2, hr_pwr_oe3, hr_pwr_oe4,
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adc_d, hr_adc_clk,
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hr_ssp_frame, hr_ssp_din, ssp_dout, hr_ssp_clk,
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hr_dbg,
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subcarrier_frequency, minor_mode
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);
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hi_simulate hs(
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pck0, ck_1356meg, ck_1356megb,
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ck_1356meg,
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hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,
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adc_d, hs_adc_clk,
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hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,
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cross_hi, cross_lo,
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hs_dbg,
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hi_simulate_mod_type
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minor_mode
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);
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hi_iso14443a hisn(
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pck0, ck_1356meg, ck_1356megb,
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hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,
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ck_1356meg,
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hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,
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adc_d, hisn_adc_clk,
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hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk,
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cross_hi, cross_lo,
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hisn_dbg,
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hi_simulate_mod_type
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minor_mode
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);
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hi_sniffer he(
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pck0, ck_1356meg, ck_1356megb,
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he_pwr_lo, he_pwr_hi, he_pwr_oe1, he_pwr_oe2, he_pwr_oe3, he_pwr_oe4,
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adc_d, he_adc_clk,
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he_ssp_frame, he_ssp_din, ssp_dout, he_ssp_clk,
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cross_hi, cross_lo,
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he_dbg,
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hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop, hi_read_rx_xcorr_quarter
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ck_1356megb,
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he_pwr_lo, he_pwr_hi, he_pwr_oe1, he_pwr_oe2, he_pwr_oe3, he_pwr_oe4,
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adc_d, he_adc_clk,
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he_ssp_frame, he_ssp_din, he_ssp_clk
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);
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hi_get_trace gt(
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ck_1356megb,
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adc_d, trace_enable, major_mode,
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gt_ssp_frame, gt_ssp_din, gt_ssp_clk
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ck_1356megb,
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adc_d, trace_enable, major_mode,
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gt_ssp_frame, gt_ssp_din, gt_ssp_clk
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);
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// Major modes:
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// 000 -- HF reader, transmitting to tag; modulation depth selectable
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// 001 -- HF reader, receiving from tag, correlating as it goes; frequency selectable
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// 010 -- HF simulated tag
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// 011 -- HF ISO14443-A
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// 100 -- HF Snoop
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// 101 -- HF get trace
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// 000 -- HF reader; subcarrier frequency and modulation depth selectable
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// 001 -- HF simulated tag
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// 010 -- HF ISO14443-A
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// 011 -- HF Snoop
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// 100 -- HF get trace
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// 111 -- everything off
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mux8 mux_ssp_clk (major_mode, ssp_clk, ht_ssp_clk, hrxc_ssp_clk, hs_ssp_clk, hisn_ssp_clk, he_ssp_clk, gt_ssp_clk, 1'b0, 1'b0);
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mux8 mux_ssp_din (major_mode, ssp_din, ht_ssp_din, hrxc_ssp_din, hs_ssp_din, hisn_ssp_din, he_ssp_din, gt_ssp_din, 1'b0, 1'b0);
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mux8 mux_ssp_frame (major_mode, ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, he_ssp_frame, gt_ssp_frame, 1'b0, 1'b0);
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mux8 mux_pwr_oe1 (major_mode, pwr_oe1, ht_pwr_oe1, hrxc_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, he_pwr_oe1, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe2 (major_mode, pwr_oe2, ht_pwr_oe2, hrxc_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, he_pwr_oe2, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe3 (major_mode, pwr_oe3, ht_pwr_oe3, hrxc_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, he_pwr_oe3, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe4 (major_mode, pwr_oe4, ht_pwr_oe4, hrxc_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, he_pwr_oe4, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_lo (major_mode, pwr_lo, ht_pwr_lo, hrxc_pwr_lo, hs_pwr_lo, hisn_pwr_lo, he_pwr_lo, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_hi (major_mode, pwr_hi, ht_pwr_hi, hrxc_pwr_hi, hs_pwr_hi, hisn_pwr_hi, he_pwr_hi, 1'b0, 1'b0, 1'b0);
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mux8 mux_adc_clk (major_mode, adc_clk, ht_adc_clk, hrxc_adc_clk, hs_adc_clk, hisn_adc_clk, he_adc_clk, 1'b0, 1'b0, 1'b0);
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mux8 mux_dbg (major_mode, dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, he_dbg, 1'b0, 1'b0, 1'b0);
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mux8 mux_ssp_clk (major_mode, ssp_clk, hr_ssp_clk, hs_ssp_clk, hisn_ssp_clk, he_ssp_clk, gt_ssp_clk, 1'b0, 1'b0, 1'b0);
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mux8 mux_ssp_din (major_mode, ssp_din, hr_ssp_din, hs_ssp_din, hisn_ssp_din, he_ssp_din, gt_ssp_din, 1'b0, 1'b0, 1'b0);
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mux8 mux_ssp_frame (major_mode, ssp_frame, hr_ssp_frame, hs_ssp_frame, hisn_ssp_frame, he_ssp_frame, gt_ssp_frame, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe1 (major_mode, pwr_oe1, hr_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, he_pwr_oe1, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe2 (major_mode, pwr_oe2, hr_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, he_pwr_oe2, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe3 (major_mode, pwr_oe3, hr_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, he_pwr_oe3, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe4 (major_mode, pwr_oe4, hr_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, he_pwr_oe4, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_lo (major_mode, pwr_lo, hr_pwr_lo, hs_pwr_lo, hisn_pwr_lo, he_pwr_lo, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_hi (major_mode, pwr_hi, hr_pwr_hi, hs_pwr_hi, hisn_pwr_hi, he_pwr_hi, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_adc_clk (major_mode, adc_clk, hr_adc_clk, hs_adc_clk, hisn_adc_clk, he_adc_clk, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_dbg (major_mode, dbg, hr_dbg, hs_dbg, hisn_dbg, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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// In all modes, let the ADC's outputs be enabled.
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assign adc_noe = 1'b0;
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|
||||
// not used
|
||||
assign miso = 1'b0;
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -14,11 +14,6 @@ module hi_get_trace(
|
|||
input [2:0] major_mode;
|
||||
output ssp_frame, ssp_din, ssp_clk;
|
||||
|
||||
// constants for some major_modes:
|
||||
`define OFF 3'b111
|
||||
`define GET_TRACE 3'b101
|
||||
|
||||
|
||||
// clock divider
|
||||
reg [6:0] clock_cnt;
|
||||
always @(negedge ck_1356megb)
|
||||
|
|
@ -30,7 +25,7 @@ end
|
|||
reg [2:0] sample_clock;
|
||||
always @(negedge ck_1356megb)
|
||||
begin
|
||||
if (sample_clock == 3'd3)
|
||||
if (sample_clock == 3'd7)
|
||||
sample_clock <= 3'd0;
|
||||
else
|
||||
sample_clock <= sample_clock + 1;
|
||||
|
|
@ -45,11 +40,11 @@ reg write_enable2;
|
|||
always @(negedge ck_1356megb)
|
||||
begin
|
||||
previous_major_mode <= major_mode;
|
||||
if (major_mode == `GET_TRACE)
|
||||
if (major_mode == `FPGA_MAJOR_MODE_HF_GET_TRACE)
|
||||
begin
|
||||
write_enable1 <= 1'b0;
|
||||
write_enable2 <= 1'b0;
|
||||
if (previous_major_mode != `GET_TRACE) // just switched into GET_TRACE mode
|
||||
if (previous_major_mode != `FPGA_MAJOR_MODE_HF_GET_TRACE) // just switched into GET_TRACE mode
|
||||
addr <= start_addr;
|
||||
if (clock_cnt == 7'd0)
|
||||
begin
|
||||
|
|
@ -59,7 +54,7 @@ begin
|
|||
addr <= addr + 1;
|
||||
end
|
||||
end
|
||||
else if (major_mode != `OFF)
|
||||
else if (major_mode != `FPGA_MAJOR_MODE_OFF)
|
||||
begin
|
||||
if (trace_enable)
|
||||
begin
|
||||
|
|
@ -92,11 +87,11 @@ begin
|
|||
start_addr <= addr;
|
||||
end
|
||||
end
|
||||
else // major_mode == `OFF
|
||||
else // major_mode == `FPGA_MAJOR_MODE_OFF
|
||||
begin
|
||||
write_enable1 <= 1'b0;
|
||||
write_enable2 <= 1'b0;
|
||||
if (previous_major_mode != `OFF && previous_major_mode != `GET_TRACE) // just switched off
|
||||
if (previous_major_mode != `FPGA_MAJOR_MODE_OFF && previous_major_mode != `FPGA_MAJOR_MODE_HF_GET_TRACE) // just switched off
|
||||
start_addr <= addr;
|
||||
end
|
||||
end
|
||||
|
|
|
|||
|
|
@ -3,29 +3,20 @@
|
|||
// Gerhard de Koning Gans, April 2008
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
// constants for the different modes:
|
||||
`define SNIFFER 3'b000
|
||||
`define TAGSIM_LISTEN 3'b001
|
||||
`define TAGSIM_MOD 3'b010
|
||||
`define READER_LISTEN 3'b011
|
||||
`define READER_MOD 3'b100
|
||||
|
||||
module hi_iso14443a(
|
||||
pck0, ck_1356meg, ck_1356megb,
|
||||
ck_1356meg,
|
||||
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
|
||||
adc_d, adc_clk,
|
||||
ssp_frame, ssp_din, ssp_dout, ssp_clk,
|
||||
cross_hi, cross_lo,
|
||||
dbg,
|
||||
mod_type
|
||||
);
|
||||
input pck0, ck_1356meg, ck_1356megb;
|
||||
input ck_1356meg;
|
||||
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
|
||||
input [7:0] adc_d;
|
||||
output adc_clk;
|
||||
input ssp_dout;
|
||||
output ssp_frame, ssp_din, ssp_clk;
|
||||
input cross_hi, cross_lo;
|
||||
output dbg;
|
||||
input [2:0] mod_type;
|
||||
|
||||
|
|
@ -151,7 +142,7 @@ begin
|
|||
end
|
||||
|
||||
// adjust internal timer counter if necessary:
|
||||
if (negedge_cnt[3:0] == 4'd13 && (mod_type == `SNIFFER || mod_type == `TAGSIM_LISTEN) && deep_modulation)
|
||||
if (negedge_cnt[3:0] == 4'd13 && (mod_type == `FPGA_HF_ISO14443A_SNIFFER || mod_type == `FPGA_HF_ISO14443A_TAGSIM_LISTEN) && deep_modulation)
|
||||
begin
|
||||
if (reader_falling_edge_time == 4'd1) // reader signal changes right after sampling. Better sample earlier next time.
|
||||
begin
|
||||
|
|
@ -185,7 +176,7 @@ reg [3:0] mod_detect_reset_time;
|
|||
|
||||
always @(negedge adc_clk)
|
||||
begin
|
||||
if (mod_type == `READER_LISTEN)
|
||||
if (mod_type == `FPGA_HF_ISO14443A_READER_LISTEN)
|
||||
// (our) reader signal changes at negedge_cnt[3:0]=9, tag response expected to start n*16+4 ticks later, further delayed by
|
||||
// 3 ticks ADC conversion. The maximum filter output (edge detected) will be detected after subcarrier zero crossing (+7 ticks).
|
||||
// To allow some timing variances, we want to have the maximum filter outputs well within the detection window, i.e.
|
||||
|
|
@ -195,7 +186,7 @@ begin
|
|||
mod_detect_reset_time <= 4'd4;
|
||||
end
|
||||
else
|
||||
if (mod_type == `SNIFFER)
|
||||
if (mod_type == `FPGA_HF_ISO14443A_SNIFFER)
|
||||
begin
|
||||
// detect a rising edge of reader's signal and sync modulation detector to the tag's answer:
|
||||
if (~pre_after_hysteresis && after_hysteresis && deep_modulation)
|
||||
|
|
@ -320,7 +311,7 @@ reg [3:0] sub_carrier_cnt;
|
|||
// response window of 1128 - 774 = 354 ticks.
|
||||
|
||||
// reset on a pause in listen mode. I.e. the counter starts when the pause is over:
|
||||
assign fdt_reset = ~after_hysteresis && mod_type == `TAGSIM_LISTEN;
|
||||
assign fdt_reset = ~after_hysteresis && mod_type == `FPGA_HF_ISO14443A_TAGSIM_LISTEN;
|
||||
|
||||
always @(negedge adc_clk)
|
||||
begin
|
||||
|
|
@ -363,7 +354,7 @@ reg mod_sig_coil;
|
|||
|
||||
always @(negedge adc_clk)
|
||||
begin
|
||||
if (mod_type == `TAGSIM_MOD) // need to take care of proper fdt timing
|
||||
if (mod_type == `FPGA_HF_ISO14443A_TAGSIM_MOD) // need to take care of proper fdt timing
|
||||
begin
|
||||
if(fdt_counter == `FDT_COUNT)
|
||||
begin
|
||||
|
|
@ -438,7 +429,7 @@ always @(negedge adc_clk)
|
|||
begin
|
||||
if (negedge_cnt[5:0] == 6'd63) // fill the buffer
|
||||
begin
|
||||
if (mod_type == `SNIFFER)
|
||||
if (mod_type == `FPGA_HF_ISO14443A_SNIFFER)
|
||||
begin
|
||||
if(deep_modulation) // a reader is sending (or there's no field at all)
|
||||
begin
|
||||
|
|
@ -455,7 +446,7 @@ begin
|
|||
end
|
||||
end
|
||||
|
||||
if(negedge_cnt[2:0] == 3'b000 && mod_type == `SNIFFER) // shift at double speed
|
||||
if(negedge_cnt[2:0] == 3'b000 && mod_type == `FPGA_HF_ISO14443A_SNIFFER) // shift at double speed
|
||||
begin
|
||||
// Don't shift if we just loaded new data, obviously.
|
||||
if(negedge_cnt[5:0] != 6'd0)
|
||||
|
|
@ -464,7 +455,7 @@ begin
|
|||
end
|
||||
end
|
||||
|
||||
if(negedge_cnt[3:0] == 4'b0000 && mod_type != `SNIFFER)
|
||||
if(negedge_cnt[3:0] == 4'b0000 && mod_type != `FPGA_HF_ISO14443A_SNIFFER)
|
||||
begin
|
||||
// Don't shift if we just loaded new data, obviously.
|
||||
if(negedge_cnt[6:0] != 7'd0)
|
||||
|
|
@ -484,8 +475,8 @@ reg ssp_frame;
|
|||
|
||||
always @(negedge adc_clk)
|
||||
begin
|
||||
if(mod_type == `SNIFFER)
|
||||
// SNIFFER mode (ssp_clk = adc_clk / 8, ssp_frame clock = adc_clk / 64)):
|
||||
if(mod_type == `FPGA_HF_ISO14443A_SNIFFER)
|
||||
// FPGA_HF_ISO14443A_SNIFFER mode (ssp_clk = adc_clk / 8, ssp_frame clock = adc_clk / 64)):
|
||||
begin
|
||||
if(negedge_cnt[2:0] == 3'd0)
|
||||
ssp_clk <= 1'b1;
|
||||
|
|
@ -505,7 +496,7 @@ begin
|
|||
if(negedge_cnt[3:0] == 4'd8)
|
||||
ssp_clk <= 1'b0;
|
||||
|
||||
if(negedge_cnt[6:0] == 7'd7) // ssp_frame rising edge indicates start of frame
|
||||
if(negedge_cnt[6:0] == 7'd7) // ssp_frame rising edge indicates start of frame, sampled on falling edge of ssp_clk
|
||||
ssp_frame <= 1'b1;
|
||||
if(negedge_cnt[6:0] == 7'd23)
|
||||
ssp_frame <= 1'b0;
|
||||
|
|
@ -525,23 +516,23 @@ begin
|
|||
if(negedge_cnt[3:0] == 4'd0)
|
||||
begin
|
||||
// What do we communicate to the ARM
|
||||
if(mod_type == `TAGSIM_LISTEN)
|
||||
if(mod_type == `FPGA_HF_ISO14443A_TAGSIM_LISTEN)
|
||||
sendbit = after_hysteresis;
|
||||
else if(mod_type == `TAGSIM_MOD)
|
||||
else if(mod_type == `FPGA_HF_ISO14443A_TAGSIM_MOD)
|
||||
/* if(fdt_counter > 11'd772) sendbit = mod_sig_coil; // huh?
|
||||
else */
|
||||
sendbit = fdt_indicator;
|
||||
else if (mod_type == `READER_LISTEN)
|
||||
else if (mod_type == `FPGA_HF_ISO14443A_READER_LISTEN)
|
||||
sendbit = curbit;
|
||||
else
|
||||
sendbit = 1'b0;
|
||||
end
|
||||
|
||||
|
||||
if(mod_type == `SNIFFER)
|
||||
if(mod_type == `FPGA_HF_ISO14443A_SNIFFER)
|
||||
// send sampled reader and tag data:
|
||||
bit_to_arm = to_arm[7];
|
||||
else if (mod_type == `TAGSIM_MOD && fdt_elapsed && temp_buffer_reset)
|
||||
else if (mod_type == `FPGA_HF_ISO14443A_TAGSIM_MOD && fdt_elapsed && temp_buffer_reset)
|
||||
// send timing information:
|
||||
bit_to_arm = to_arm[7];
|
||||
else
|
||||
|
|
@ -554,22 +545,22 @@ end
|
|||
|
||||
assign ssp_din = bit_to_arm;
|
||||
|
||||
// Subcarrier (adc_clk/16, for TAGSIM_MOD only).
|
||||
// Subcarrier (adc_clk/16, for FPGA_HF_ISO14443A_TAGSIM_MOD only).
|
||||
wire sub_carrier;
|
||||
assign sub_carrier = ~sub_carrier_cnt[3];
|
||||
|
||||
// in READER_MOD: drop carrier for mod_sig_coil==1 (pause); in READER_LISTEN: carrier always on; in other modes: carrier always off
|
||||
assign pwr_hi = (ck_1356megb & (((mod_type == `READER_MOD) & ~mod_sig_coil) || (mod_type == `READER_LISTEN)));
|
||||
// in FPGA_HF_ISO14443A_READER_MOD: drop carrier for mod_sig_coil==1 (pause); in FPGA_HF_ISO14443A_READER_LISTEN: carrier always on; in other modes: carrier always off
|
||||
assign pwr_hi = (ck_1356meg & (((mod_type == `FPGA_HF_ISO14443A_READER_MOD) & ~mod_sig_coil) || (mod_type == `FPGA_HF_ISO14443A_READER_LISTEN)));
|
||||
|
||||
|
||||
// Enable HF antenna drivers:
|
||||
assign pwr_oe1 = 1'b0;
|
||||
assign pwr_oe3 = 1'b0;
|
||||
|
||||
// TAGSIM_MOD: short circuit antenna with different resistances (modulated by sub_carrier modulated by mod_sig_coil)
|
||||
// FPGA_HF_ISO14443A_TAGSIM_MOD: short circuit antenna with different resistances (modulated by sub_carrier modulated by mod_sig_coil)
|
||||
// for pwr_oe4 = 1 (tristate): antenna load = 10k || 33 = 32,9 Ohms
|
||||
// for pwr_oe4 = 0 (active): antenna load = 10k || 33 || 33 = 16,5 Ohms
|
||||
assign pwr_oe4 = mod_sig_coil & sub_carrier & (mod_type == `TAGSIM_MOD);
|
||||
assign pwr_oe4 = mod_sig_coil & sub_carrier & (mod_type == `FPGA_HF_ISO14443A_TAGSIM_MOD);
|
||||
|
||||
// This is all LF, so doesn't matter.
|
||||
assign pwr_oe2 = 1'b0;
|
||||
|
|
|
|||
|
|
@ -1,78 +0,0 @@
|
|||
//-----------------------------------------------------------------------------
|
||||
// The way that we connect things when transmitting a command to an ISO
|
||||
// 15693 tag, using 100% modulation only for now.
|
||||
//
|
||||
// Jonathan Westhues, April 2006
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
module hi_read_tx(
|
||||
pck0, ck_1356meg, ck_1356megb,
|
||||
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
|
||||
adc_d, adc_clk,
|
||||
ssp_frame, ssp_din, ssp_dout, ssp_clk,
|
||||
cross_hi, cross_lo,
|
||||
dbg,
|
||||
shallow_modulation
|
||||
);
|
||||
input pck0, ck_1356meg, ck_1356megb;
|
||||
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
|
||||
input [7:0] adc_d;
|
||||
output adc_clk;
|
||||
input ssp_dout;
|
||||
output ssp_frame, ssp_din, ssp_clk;
|
||||
input cross_hi, cross_lo;
|
||||
output dbg;
|
||||
input shallow_modulation;
|
||||
|
||||
// low frequency outputs, not relevant
|
||||
assign pwr_lo = 1'b0;
|
||||
assign pwr_oe2 = 1'b0;
|
||||
|
||||
// The high-frequency stuff. For now, for testing, just bring out the carrier,
|
||||
// and allow the ARM to modulate it over the SSP.
|
||||
reg pwr_hi;
|
||||
reg pwr_oe1;
|
||||
reg pwr_oe3;
|
||||
reg pwr_oe4;
|
||||
|
||||
always @(ck_1356megb or ssp_dout or shallow_modulation)
|
||||
begin
|
||||
if(shallow_modulation)
|
||||
begin
|
||||
pwr_hi <= ck_1356megb;
|
||||
pwr_oe1 <= 1'b0;
|
||||
pwr_oe3 <= 1'b0;
|
||||
pwr_oe4 <= ssp_dout;
|
||||
end
|
||||
else
|
||||
begin
|
||||
pwr_hi <= ck_1356megb & ~ssp_dout;
|
||||
pwr_oe1 <= 1'b0;
|
||||
pwr_oe3 <= 1'b0;
|
||||
pwr_oe4 <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// Then just divide the 13.56 MHz clock down to produce appropriate clocks
|
||||
// for the synchronous serial port.
|
||||
|
||||
reg [6:0] hi_div_by_128;
|
||||
|
||||
always @(posedge ck_1356meg)
|
||||
hi_div_by_128 <= hi_div_by_128 + 1;
|
||||
|
||||
assign ssp_clk = hi_div_by_128[6];
|
||||
|
||||
reg [2:0] hi_byte_div;
|
||||
|
||||
always @(negedge ssp_clk)
|
||||
hi_byte_div <= hi_byte_div + 1;
|
||||
|
||||
assign ssp_frame = (hi_byte_div == 3'b000);
|
||||
|
||||
assign ssp_din = 1'b0;
|
||||
|
||||
assign dbg = ssp_frame;
|
||||
|
||||
endmodule
|
||||
|
|
@ -3,35 +3,25 @@
|
|||
// Jonathan Westhues, April 2006
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
module hi_read_rx_xcorr(
|
||||
pck0, ck_1356meg, ck_1356megb,
|
||||
module hi_reader(
|
||||
ck_1356meg,
|
||||
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
|
||||
adc_d, adc_clk,
|
||||
ssp_frame, ssp_din, ssp_dout, ssp_clk,
|
||||
cross_hi, cross_lo,
|
||||
dbg,
|
||||
xcorr_is_848, snoop, xcorr_quarter_freq, hi_read_rx_xcorr_amplitude
|
||||
subcarrier_frequency, minor_mode
|
||||
);
|
||||
input pck0, ck_1356meg, ck_1356megb;
|
||||
input ck_1356meg;
|
||||
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
|
||||
input [7:0] adc_d;
|
||||
output adc_clk;
|
||||
input ssp_dout;
|
||||
output ssp_frame, ssp_din, ssp_clk;
|
||||
input cross_hi, cross_lo;
|
||||
output dbg;
|
||||
input xcorr_is_848, snoop, xcorr_quarter_freq, hi_read_rx_xcorr_amplitude;
|
||||
input [1:0] subcarrier_frequency;
|
||||
input [2:0] minor_mode;
|
||||
|
||||
// Carrier is steady on through this, unless we're snooping.
|
||||
assign pwr_hi = ck_1356megb & (~snoop);
|
||||
assign pwr_oe1 = 1'b0;
|
||||
assign pwr_oe3 = 1'b0;
|
||||
assign pwr_oe4 = 1'b0;
|
||||
// Unused.
|
||||
assign pwr_lo = 1'b0;
|
||||
assign pwr_oe2 = 1'b0;
|
||||
|
||||
assign adc_clk = ck_1356megb; // sample frequency is 13,56 MHz
|
||||
assign adc_clk = ck_1356meg; // sample frequency is 13,56 MHz
|
||||
|
||||
// When we're a reader, we just need to do the BPSK demod; but when we're an
|
||||
// eavesdropper, we also need to pick out the commands sent by the reader,
|
||||
|
|
@ -71,7 +61,8 @@ begin
|
|||
corr_i_cnt <= corr_i_cnt + 1;
|
||||
end
|
||||
|
||||
// And a couple of registers in which to accumulate the correlations. From the 64 samples
|
||||
|
||||
// A couple of registers in which to accumulate the correlations. From the 64 samples
|
||||
// we would add at most 32 times the difference between unmodulated and modulated signal. It should
|
||||
// be safe to assume that a tag will not be able to modulate the carrier signal by more than 25%.
|
||||
// 32 * 255 * 0,25 = 2040, which can be held in 11 bits. Add 1 bit for sign.
|
||||
|
|
@ -84,18 +75,13 @@ reg signed [13:0] corr_q_accum;
|
|||
reg signed [7:0] corr_i_out;
|
||||
reg signed [7:0] corr_q_out;
|
||||
|
||||
// clock and frame signal for communication to ARM
|
||||
reg ssp_clk;
|
||||
reg ssp_frame;
|
||||
|
||||
|
||||
|
||||
// the amplitude of the subcarrier is sqrt(ci^2 + cq^2).
|
||||
// approximate by amplitude = max(|ci|,|cq|) + 1/2*min(|ci|,|cq|)
|
||||
reg [13:0] corr_amplitude, abs_ci, abs_cq, max_ci_cq, min_ci_cq;
|
||||
reg [13:0] corr_amplitude, abs_ci, abs_cq, max_ci_cq;
|
||||
reg [12:0] min_ci_cq_2; // min_ci_cq / 2
|
||||
|
||||
|
||||
always @(corr_i_accum or corr_q_accum)
|
||||
always @(*)
|
||||
begin
|
||||
if (corr_i_accum[13] == 1'b0)
|
||||
abs_ci <= corr_i_accum;
|
||||
|
|
@ -110,15 +96,15 @@ begin
|
|||
if (abs_ci > abs_cq)
|
||||
begin
|
||||
max_ci_cq <= abs_ci;
|
||||
min_ci_cq <= abs_cq;
|
||||
min_ci_cq_2 <= abs_cq / 2;
|
||||
end
|
||||
else
|
||||
begin
|
||||
max_ci_cq <= abs_cq;
|
||||
min_ci_cq <= abs_ci;
|
||||
min_ci_cq_2 <= abs_ci / 2;
|
||||
end
|
||||
|
||||
corr_amplitude <= max_ci_cq + min_ci_cq/2;
|
||||
corr_amplitude <= max_ci_cq + min_ci_cq_2;
|
||||
|
||||
end
|
||||
|
||||
|
|
@ -127,14 +113,14 @@ end
|
|||
reg subcarrier_I;
|
||||
reg subcarrier_Q;
|
||||
|
||||
always @(corr_i_cnt or xcorr_is_848 or xcorr_quarter_freq)
|
||||
always @(*)
|
||||
begin
|
||||
if (xcorr_is_848 & ~xcorr_quarter_freq) // 848 kHz
|
||||
if (subcarrier_frequency == `FPGA_HF_READER_SUBCARRIER_848_KHZ)
|
||||
begin
|
||||
subcarrier_I = ~corr_i_cnt[3];
|
||||
subcarrier_Q = ~(corr_i_cnt[3] ^ corr_i_cnt[2]);
|
||||
end
|
||||
else if (xcorr_is_848 & xcorr_quarter_freq) // 212 kHz
|
||||
else if (subcarrier_frequency == `FPGA_HF_READER_SUBCARRIER_212_KHZ)
|
||||
begin
|
||||
subcarrier_I = ~corr_i_cnt[5];
|
||||
subcarrier_Q = ~(corr_i_cnt[5] ^ corr_i_cnt[4]);
|
||||
|
|
@ -155,62 +141,56 @@ begin
|
|||
// resulting amplitude to send out later over the SSP.
|
||||
if(corr_i_cnt == 6'd0)
|
||||
begin
|
||||
if(snoop)
|
||||
if (minor_mode == `FPGA_HF_READER_MODE_SNIFF_AMPLITUDE)
|
||||
begin
|
||||
if (hi_read_rx_xcorr_amplitude)
|
||||
begin
|
||||
// send amplitude plus 2 bits reader signal
|
||||
corr_i_out <= corr_amplitude[13:6];
|
||||
corr_q_out <= {corr_amplitude[5:0], after_hysteresis_prev_prev, after_hysteresis_prev};
|
||||
end
|
||||
else
|
||||
begin
|
||||
// Send 7 most significant bits of in phase tag signal (signed), plus 1 bit reader signal
|
||||
if (corr_i_accum[13:11] == 3'b000 || corr_i_accum[13:11] == 3'b111)
|
||||
corr_i_out <= {corr_i_accum[11:5], after_hysteresis_prev_prev};
|
||||
else // truncate to maximum value
|
||||
if (corr_i_accum[13] == 1'b0)
|
||||
corr_i_out <= {7'b0111111, after_hysteresis_prev_prev};
|
||||
else
|
||||
corr_i_out <= {7'b1000000, after_hysteresis_prev_prev};
|
||||
// Send 7 most significant bits of quadrature phase tag signal (signed), plus 1 bit reader signal
|
||||
if (corr_q_accum[13:11] == 3'b000 || corr_q_accum[13:11] == 3'b111)
|
||||
corr_q_out <= {corr_q_accum[11:5], after_hysteresis_prev};
|
||||
else // truncate to maximum value
|
||||
if (corr_q_accum[13] == 1'b0)
|
||||
corr_q_out <= {7'b0111111, after_hysteresis_prev};
|
||||
else
|
||||
corr_q_out <= {7'b1000000, after_hysteresis_prev};
|
||||
end
|
||||
end
|
||||
else
|
||||
// send amplitude plus 2 bits reader signal
|
||||
corr_i_out <= corr_amplitude[13:6];
|
||||
corr_q_out <= {corr_amplitude[5:0], after_hysteresis_prev_prev, after_hysteresis_prev};
|
||||
end
|
||||
else if (minor_mode == `FPGA_HF_READER_MODE_SNIFF_IQ)
|
||||
begin
|
||||
// Send 7 most significant bits of in phase tag signal (signed), plus 1 bit reader signal
|
||||
if (corr_i_accum[13:11] == 3'b000 || corr_i_accum[13:11] == 3'b111)
|
||||
corr_i_out <= {corr_i_accum[11:5], after_hysteresis_prev_prev};
|
||||
else // truncate to maximum value
|
||||
if (corr_i_accum[13] == 1'b0)
|
||||
corr_i_out <= {7'b0111111, after_hysteresis_prev_prev};
|
||||
else
|
||||
corr_i_out <= {7'b1000000, after_hysteresis_prev_prev};
|
||||
// Send 7 most significant bits of quadrature phase tag signal (signed), plus 1 bit reader signal
|
||||
if (corr_q_accum[13:11] == 3'b000 || corr_q_accum[13:11] == 3'b111)
|
||||
corr_q_out <= {corr_q_accum[11:5], after_hysteresis_prev};
|
||||
else // truncate to maximum value
|
||||
if (corr_q_accum[13] == 1'b0)
|
||||
corr_q_out <= {7'b0111111, after_hysteresis_prev};
|
||||
else
|
||||
corr_q_out <= {7'b1000000, after_hysteresis_prev};
|
||||
end
|
||||
else if (minor_mode == `FPGA_HF_READER_MODE_RECEIVE_AMPLITUDE)
|
||||
begin
|
||||
if (hi_read_rx_xcorr_amplitude)
|
||||
begin
|
||||
// send amplitude
|
||||
corr_i_out <= {2'b00, corr_amplitude[13:8]};
|
||||
corr_q_out <= corr_amplitude[7:0];
|
||||
end
|
||||
else
|
||||
begin
|
||||
// Send 8 bits of in phase tag signal
|
||||
if (corr_i_accum[13:11] == 3'b000 || corr_i_accum[13:11] == 3'b111)
|
||||
corr_i_out <= corr_i_accum[11:4];
|
||||
else // truncate to maximum value
|
||||
if (corr_i_accum[13] == 1'b0)
|
||||
corr_i_out <= 8'b01111111;
|
||||
else
|
||||
corr_i_out <= 8'b10000000;
|
||||
// Send 8 bits of quadrature phase tag signal
|
||||
if (corr_q_accum[13:11] == 3'b000 || corr_q_accum[13:11] == 3'b111)
|
||||
corr_q_out <= corr_q_accum[11:4];
|
||||
else // truncate to maximum value
|
||||
if (corr_q_accum[13] == 1'b0)
|
||||
corr_q_out <= 8'b01111111;
|
||||
else
|
||||
corr_q_out <= 8'b10000000;
|
||||
end
|
||||
end
|
||||
// send amplitude
|
||||
corr_i_out <= {2'b00, corr_amplitude[13:8]};
|
||||
corr_q_out <= corr_amplitude[7:0];
|
||||
end
|
||||
else if (minor_mode == `FPGA_HF_READER_MODE_RECEIVE_IQ)
|
||||
begin
|
||||
// Send 8 bits of in phase tag signal
|
||||
if (corr_i_accum[13:11] == 3'b000 || corr_i_accum[13:11] == 3'b111)
|
||||
corr_i_out <= corr_i_accum[11:4];
|
||||
else // truncate to maximum value
|
||||
if (corr_i_accum[13] == 1'b0)
|
||||
corr_i_out <= 8'b01111111;
|
||||
else
|
||||
corr_i_out <= 8'b10000000;
|
||||
// Send 8 bits of quadrature phase tag signal
|
||||
if (corr_q_accum[13:11] == 3'b000 || corr_q_accum[13:11] == 3'b111)
|
||||
corr_q_out <= corr_q_accum[11:4];
|
||||
else // truncate to maximum value
|
||||
if (corr_q_accum[13] == 1'b0)
|
||||
corr_q_out <= 8'b01111111;
|
||||
else
|
||||
corr_q_out <= 8'b10000000;
|
||||
end
|
||||
|
||||
// for each Q/I pair report two reader signal samples when sniffing. Store the 1st.
|
||||
after_hysteresis_prev_prev <= after_hysteresis;
|
||||
|
|
@ -241,12 +221,8 @@ begin
|
|||
// ssp_clk should be the adc_clk divided by 64/16 = 4.
|
||||
// ssp_clk frequency = 13,56MHz / 4 = 3.39MHz
|
||||
|
||||
if(corr_i_cnt[1:0] == 2'b10)
|
||||
ssp_clk <= 1'b0;
|
||||
|
||||
if(corr_i_cnt[1:0] == 2'b00)
|
||||
begin
|
||||
ssp_clk <= 1'b1;
|
||||
// Don't shift if we just loaded new data, obviously.
|
||||
if(corr_i_cnt != 6'd0)
|
||||
begin
|
||||
|
|
@ -255,17 +231,70 @@ begin
|
|||
end
|
||||
end
|
||||
|
||||
// set ssp_frame signal for corr_i_cnt = 0..3
|
||||
// (send one frame with 16 Bits)
|
||||
if(corr_i_cnt[5:2] == 4'b0000)
|
||||
ssp_frame = 1'b1;
|
||||
else
|
||||
ssp_frame = 1'b0;
|
||||
|
||||
end
|
||||
|
||||
|
||||
// ssp clock and frame signal for communication to and from ARM
|
||||
reg ssp_clk;
|
||||
reg ssp_frame;
|
||||
|
||||
always @(negedge adc_clk)
|
||||
begin
|
||||
if (corr_i_cnt[1:0] == 2'b00)
|
||||
ssp_clk <= 1'b1;
|
||||
if (corr_i_cnt[1:0] == 2'b10)
|
||||
ssp_clk <= 1'b0;
|
||||
|
||||
// set ssp_frame signal for corr_i_cnt = 1..3
|
||||
// (send one frame with 16 Bits)
|
||||
if (corr_i_cnt == 6'd2)
|
||||
ssp_frame <= 1'b1;
|
||||
if (corr_i_cnt == 6'd14)
|
||||
ssp_frame <= 1'b0;
|
||||
end
|
||||
|
||||
|
||||
assign ssp_din = corr_i_out[7];
|
||||
|
||||
|
||||
// Antenna drivers
|
||||
reg pwr_hi, pwr_oe4;
|
||||
|
||||
always @(*)
|
||||
begin
|
||||
if (minor_mode == `FPGA_HF_READER_MODE_SEND_SHALLOW_MOD)
|
||||
begin
|
||||
pwr_hi = ck_1356meg;
|
||||
pwr_oe4 = ssp_dout;
|
||||
end
|
||||
else if (minor_mode == `FPGA_HF_READER_MODE_SEND_FULL_MOD)
|
||||
begin
|
||||
pwr_hi = ck_1356meg & ~ssp_dout;
|
||||
pwr_oe4 = 1'b0;
|
||||
end
|
||||
else if (minor_mode == `FPGA_HF_READER_MODE_SNIFF_IQ
|
||||
|| minor_mode == `FPGA_HF_READER_MODE_SNIFF_AMPLITUDE
|
||||
|| minor_mode == `FPGA_HF_READER_MODE_SNIFF_PHASE)
|
||||
begin
|
||||
pwr_hi = 1'b0;
|
||||
pwr_oe4 = 1'b0;
|
||||
end
|
||||
else // receiving from tag
|
||||
begin
|
||||
pwr_hi = ck_1356meg;
|
||||
pwr_oe4 = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// always on
|
||||
assign pwr_oe1 = 1'b0;
|
||||
assign pwr_oe3 = 1'b0;
|
||||
|
||||
// Unused.
|
||||
assign pwr_lo = 1'b0;
|
||||
assign pwr_oe2 = 1'b0;
|
||||
|
||||
// Debug Output
|
||||
assign dbg = corr_i_cnt[3];
|
||||
|
||||
endmodule
|
||||
|
|
@ -16,29 +16,20 @@
|
|||
// Jonathan Westhues, October 2006
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
// possible mod_types:
|
||||
`define NO_MODULATION 3'b000
|
||||
`define MODULATE_BPSK 3'b001
|
||||
`define MODULATE_212K 3'b010
|
||||
`define MODULATE_424K 3'b100
|
||||
`define MODULATE_424K_8BIT 3'b101
|
||||
|
||||
module hi_simulate(
|
||||
pck0, ck_1356meg, ck_1356megb,
|
||||
ck_1356meg,
|
||||
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
|
||||
adc_d, adc_clk,
|
||||
ssp_frame, ssp_din, ssp_dout, ssp_clk,
|
||||
cross_hi, cross_lo,
|
||||
dbg,
|
||||
mod_type
|
||||
);
|
||||
input pck0, ck_1356meg, ck_1356megb;
|
||||
input ck_1356meg;
|
||||
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
|
||||
input [7:0] adc_d;
|
||||
output adc_clk;
|
||||
input ssp_dout;
|
||||
output ssp_frame, ssp_din, ssp_clk;
|
||||
input cross_hi, cross_lo;
|
||||
output dbg;
|
||||
input [2:0] mod_type;
|
||||
|
||||
|
|
@ -49,8 +40,8 @@ assign adc_clk = ck_1356meg;
|
|||
|
||||
always @(negedge adc_clk)
|
||||
begin
|
||||
if(& adc_d[7:5]) after_hysteresis = 1'b1;
|
||||
else if(~(| adc_d[7:5])) after_hysteresis = 1'b0;
|
||||
if(& adc_d[7:5]) after_hysteresis = 1'b1; // if (adc_d >= 224)
|
||||
else if(~(| adc_d[7:5])) after_hysteresis = 1'b0; // if (adc_d <= 31)
|
||||
end
|
||||
|
||||
|
||||
|
|
@ -65,10 +56,10 @@ reg ssp_clk;
|
|||
|
||||
always @(negedge adc_clk)
|
||||
begin
|
||||
if(mod_type == `MODULATE_424K_8BIT)
|
||||
if(mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K_8BIT)
|
||||
// Get bit every at 53KHz (every 8th carrier bit of 424kHz)
|
||||
ssp_clk <= ssp_clk_divider[7];
|
||||
else if(mod_type == `MODULATE_212K)
|
||||
else if(mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
|
||||
// Get next bit at 212kHz
|
||||
ssp_clk <= ssp_clk_divider[5];
|
||||
else
|
||||
|
|
@ -92,7 +83,7 @@ always @(negedge ssp_clk)
|
|||
|
||||
reg ssp_frame;
|
||||
always @(ssp_frame_divider_to_arm or ssp_frame_divider_from_arm or mod_type)
|
||||
if(mod_type == `NO_MODULATION) // not modulating, so listening, to ARM
|
||||
if(mod_type == `FPGA_HF_SIMULATOR_NO_MODULATION) // not modulating, so listening, to ARM
|
||||
ssp_frame = (ssp_frame_divider_to_arm == 3'b000);
|
||||
else
|
||||
ssp_frame = (ssp_frame_divider_from_arm == 3'b000);
|
||||
|
|
@ -104,14 +95,14 @@ always @(posedge ssp_clk)
|
|||
|
||||
// Modulating carrier frequency is fc/64 (212kHz) to fc/16 (848kHz). Reuse ssp_clk divider for that.
|
||||
reg modulating_carrier;
|
||||
always @(mod_type or ssp_clk or ssp_dout)
|
||||
if (mod_type == `NO_MODULATION)
|
||||
always @(*)
|
||||
if (mod_type == `FPGA_HF_SIMULATOR_NO_MODULATION)
|
||||
modulating_carrier <= 1'b0; // no modulation
|
||||
else if (mod_type == `MODULATE_BPSK)
|
||||
else if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_BPSK)
|
||||
modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK
|
||||
else if (mod_type == `MODULATE_212K)
|
||||
else if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
|
||||
modulating_carrier <= ssp_dout & ssp_clk_divider[5]; // switch 212kHz subcarrier on/off
|
||||
else if (mod_type == `MODULATE_424K || mod_type == `MODULATE_424K_8BIT)
|
||||
else if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K || mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K_8BIT)
|
||||
modulating_carrier <= ssp_dout & ssp_clk_divider[4]; // switch 424kHz modulation on/off
|
||||
else
|
||||
modulating_carrier <= 1'b0; // yet unused
|
||||
|
|
|
|||
|
|
@ -1,21 +1,14 @@
|
|||
module hi_sniffer(
|
||||
pck0, ck_1356meg, ck_1356megb,
|
||||
ck_1356meg,
|
||||
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
|
||||
adc_d, adc_clk,
|
||||
ssp_frame, ssp_din, ssp_dout, ssp_clk,
|
||||
cross_hi, cross_lo,
|
||||
dbg,
|
||||
xcorr_is_848, snoop, xcorr_quarter_freq // not used.
|
||||
ssp_frame, ssp_din, ssp_clk
|
||||
);
|
||||
input pck0, ck_1356meg, ck_1356megb;
|
||||
input ck_1356meg;
|
||||
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
|
||||
input [7:0] adc_d;
|
||||
output adc_clk;
|
||||
input ssp_dout;
|
||||
output ssp_frame, ssp_din, ssp_clk;
|
||||
input cross_hi, cross_lo;
|
||||
output dbg;
|
||||
input xcorr_is_848, snoop, xcorr_quarter_freq; // not used.
|
||||
|
||||
// We are only snooping, all off.
|
||||
assign pwr_hi = 1'b0;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue