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fix 'hf iclass sim':

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* chg to reader command decoder in iso15693.c (require no modulation before SOF)
* add 'has_been_low_for' logic to hi_simulate.v (same as in other FPGA modes, default to "no modulation")
* add simulation of chip status (IDLE, ACTIVE, SELECTED, HALTED)
* check ACSN on SELECT
* add simulation of RESELECT
* always check length of reader commands
* fix printing of NR, MAC in sim 2 mode
* fix response length to CHECK command
This commit is contained in:
pwpiwi 2019-09-21 11:58:51 +02:00
commit 5b12974a7f
5 changed files with 238 additions and 157 deletions
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fpga/fpga_hf.bit
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24
fpga/hi_simulate.v
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@ -33,15 +33,33 @@ module hi_simulate(
output dbg;
input [2:0] mod_type;
assign adc_clk = ck_1356meg;
// The comparator with hysteresis on the output from the peak detector.
reg after_hysteresis;
assign adc_clk = ck_1356meg;
reg [11:0] has_been_low_for;
always @(negedge adc_clk)
begin
if(& adc_d[7:5]) after_hysteresis = 1'b1; // if (adc_d >= 224)
else if(~(| adc_d[7:5])) after_hysteresis = 1'b0; // if (adc_d <= 31)
if (& adc_d[7:5]) after_hysteresis <= 1'b1; // if (adc_d >= 224)
else if (~(| adc_d[7:5])) after_hysteresis <= 1'b0; // if (adc_d <= 31)
if (adc_d >= 224)
begin
has_been_low_for <= 12'd0;
end
else
begin
if (has_been_low_for == 12'd4095)
begin
has_been_low_for <= 12'd0;
after_hysteresis <= 1'b1;
end
else
begin
has_been_low_for <= has_been_low_for + 1;
end
end
end