fix hitag functions (issue #798) (#800)

* ... and whitespace formating

armsrc/apps.h

@@ -161,18 +161,6 @@ void iClass_Dump(uint8_t blockno, uint8_t numblks);
 void iClass_Clone(uint8_t startblock, uint8_t endblock, uint8_t *data);
 void iClass_ReadCheck(uint8_t	blockNo, uint8_t keyType);
 
-// hitag2.h
-void SnoopHitag(uint32_t type);
-void SimulateHitagTag(bool tag_mem_supplied, byte_t* data);
-void ReaderHitag(hitag_function htf, hitag_data* htd);
-void WriterHitag(hitag_function htf, hitag_data* htd, int page);
-
-//hitagS.h
-void ReadHitagSCmd(hitag_function htf, hitag_data* htd, uint64_t startPage, uint64_t tagMode, bool readBlock);
-void SimulateHitagSTag(bool tag_mem_supplied, byte_t* data);
-void WritePageHitagS(hitag_function htf, hitag_data* htd,int page);
-void check_challenges_cmd(bool file_given, byte_t* data, uint64_t tagMode);
-
 // cmd.h
 bool cmd_receive(UsbCommand* cmd);
 bool cmd_send(uint32_t cmd, uint32_t arg0, uint32_t arg1, uint32_t arg2, void* data, size_t len);

armsrc/hitag2.c

@@ -16,10 +16,12 @@
 // (c) 2012 Roel Verdult
 //-----------------------------------------------------------------------------
 
+#include "hitag2.h"
+
 #include "proxmark3.h"
 #include "apps.h"
 #include "util.h"
-#include "hitag2.h"
+#include "hitag.h"
 #include "string.h"
 #include "BigBuf.h"
 #include "fpgaloader.h"
@@ -854,7 +856,7 @@ void SnoopHitag(uint32_t type) {
 	// Disable timer during configuration
 	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
 
-	// Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
+	// TC1: Capture mode, default timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
 	// external trigger rising edge, load RA on rising edge of TIOA.
 	uint32_t t1_channel_mode = AT91C_TC_CLKS_TIMER_DIV1_CLOCK | AT91C_TC_ETRGEDG_BOTH | AT91C_TC_ABETRG | AT91C_TC_LDRA_BOTH;
 	AT91C_BASE_TC1->TC_CMR = t1_channel_mode;
@@ -1083,9 +1085,13 @@ void SimulateHitagTag(bool tag_mem_supplied, byte_t* data) {
 	AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;
 
 	// Disable timer during configuration
+	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
 	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
 
-	// Capture mode, default timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
+	// TC0: Capture mode, default timer source = MCK/2 (TIMER_CLOCK1), no triggers
+	AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK;
+
+	// TC1: Capture mode, default timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
 	// external trigger rising edge, load RA on rising edge of TIOA.
 	AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK | AT91C_TC_ETRGEDG_RISING | AT91C_TC_ABETRG | AT91C_TC_LDRA_RISING;
 
@@ -1311,9 +1317,13 @@ void ReaderHitag(hitag_function htf, hitag_data* htd) {
 	AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;
 
 	// Disable timer during configuration
+	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
 	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
 
-	// Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
+	// TC0: Capture mode, default timer source = MCK/2 (TIMER_CLOCK1), no triggers
+	AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK;
+
+	// TC1: Capture mode, default timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
 	// external trigger rising edge, load RA on falling edge of TIOA.
 	AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK | AT91C_TC_ETRGEDG_FALLING | AT91C_TC_ABETRG | AT91C_TC_LDRA_FALLING;
 
@@ -1604,9 +1614,13 @@ void WriterHitag(hitag_function htf, hitag_data* htd, int page) {
 	AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;
 
 	// Disable timer during configuration
+	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
 	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
 
-	// Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
+	// TC0: Capture mode, default timer source = MCK/2 (TIMER_CLOCK1), no triggers
+	AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK;
+
+	// TC1: Capture mode, default timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
 	// external trigger rising edge, load RA on falling edge of TIOA.
 	AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK | AT91C_TC_ETRGEDG_FALLING | AT91C_TC_ABETRG | AT91C_TC_LDRA_FALLING;
 

armsrc/hitag2.h

@@ -0,0 +1,24 @@
+//-----------------------------------------------------------------------------
+// This code is licensed to you under the terms of the GNU GPL, version 2 or,
+// at your option, any later version. See the LICENSE.txt file for the text of
+// the license.
+//-----------------------------------------------------------------------------
+// Hitag2 emulation
+//
+// (c) 2009 Henryk Plötz <henryk@ploetzli.ch>
+// (c) 2012 Roel Verdult
+//-----------------------------------------------------------------------------
+
+#ifndef HITAG2_H__
+#define HITAG2_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "hitag.h"
+
+void SnoopHitag(uint32_t type);
+void SimulateHitagTag(bool tag_mem_supplied, uint8_t* data);
+void ReaderHitag(hitag_function htf, hitag_data* htd);
+void WriterHitag(hitag_function htf, hitag_data* htd, int page);
+
+#endif

armsrc/hitagS.c

@@ -12,12 +12,13 @@
 //-----------------------------------------------------------------------------
 
 
+#include "hitagS.h"
+
 #include <stdlib.h>
 #include "proxmark3.h"
 #include "apps.h"
 #include "util.h"
-#include "hitagS.h"
+#include "hitag.h"
-#include "hitag2.h"
 #include "string.h"
 #include "BigBuf.h"
 #include "fpgaloader.h"
@@ -1535,9 +1536,13 @@ void SimulateHitagSTag(bool tag_mem_supplied, byte_t* data) {
 	AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;
 
 	// Disable timer during configuration
+	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
 	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
 
-	// Capture mode, default timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
+	// TC0: Capture mode, default timer source = MCK/2 (TIMER_CLOCK1), no triggers
+	AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK;
+
+	// TC1: Capture mode, default timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
 	// external trigger rising edge, load RA on rising edge of TIOA.
 	AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK | AT91C_TC_ETRGEDG_RISING | AT91C_TC_ABETRG | AT91C_TC_LDRA_RISING;
 
@@ -1708,10 +1713,10 @@ void ReadHitagSintern(hitag_function htf, hitag_data* htd, stype tagMode, int st
 
 
 	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
-// Reset the return status
+	// Reset the return status
 	bSuccessful = false;
 
-// Clean up trace and prepare it for storing frames
+	// Clean up trace and prepare it for storing frames
 	set_tracing(true);
 	clear_trace();
 
@@ -1719,43 +1724,47 @@ void ReadHitagSintern(hitag_function htf, hitag_data* htd, stype tagMode, int st
 
 	LED_D_ON();
 
-// Configure output and enable pin that is connected to the FPGA (for modulating)
+	// Configure output and enable pin that is connected to the FPGA (for modulating)
 	AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
 	AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
 
-// Set fpga in edge detect with reader field, we can modulate as reader now
+	// Set fpga in edge detect with reader field, we can modulate as reader now
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
 
-// Set Frequency divisor which will drive the FPGA and analog mux selection
+	// Set Frequency divisor which will drive the FPGA and analog mux selection
 	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95);                  //125Khz
 	SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
 	RELAY_OFF();
 
-// Disable modulation at default, which means enable the field
+	// Disable modulation at default, which means enable the field
 	LOW(GPIO_SSC_DOUT);
 
-// Give it a bit of time for the resonant antenna to settle.
+	// Give it a bit of time for the resonant antenna to settle.
 	SpinDelay(30);
 
-// Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
+	// Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
 	AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0);
 
-// Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the tag frames
+	// Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the tag frames
 	AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
 	AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;
 
-// Disable timer during configuration
+	// Disable timer during configuration
+	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
 	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
 
-// Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
+	// TC0: Capture mode, default timer source = MCK/2 (TIMER_CLOCK1), no triggers
-// external trigger rising edge, load RA on falling edge of TIOA.
+	AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK;
+
+	// TC1: Capture mode, default timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
+	// external trigger rising edge, load RA on falling edge of TIOA.
 	AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK | AT91C_TC_ETRGEDG_FALLING | AT91C_TC_ABETRG | AT91C_TC_LDRA_FALLING;
 
-// Enable and reset counters
+	// Enable and reset counters
 	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 
-// Reset the received frame, frame count and timing info
+	// Reset the received frame, frame count and timing info
 	frame_count = 0;
 	response = 0;
 	lastbit = 1;
@@ -1940,13 +1949,13 @@ void WritePageHitagS(hitag_function htf, hitag_data* htd,int page_) {
 	Dbprintf("Page: %d",page_);
 	Dbprintf("DATA: %02X %02X %02X %02X", data[0], data[1], data[2], data[3]);
 	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
-// Reset the return status
+	// Reset the return status
 	bSuccessful = false;
 
 	tag.pstate = READY;
 	tag.tstate = NO_OP;
 
-// Clean up trace and prepare it for storing frames
+	// Clean up trace and prepare it for storing frames
 	set_tracing(true);
 	clear_trace();
 
@@ -1954,45 +1963,49 @@ void WritePageHitagS(hitag_function htf, hitag_data* htd,int page_) {
 
 	LED_D_ON();
 
-// Configure output and enable pin that is connected to the FPGA (for modulating)
+	// Configure output and enable pin that is connected to the FPGA (for modulating)
 	AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
 	AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
 
-// Set fpga in edge detect with reader field, we can modulate as reader now
+	// Set fpga in edge detect with reader field, we can modulate as reader now
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
 
-// Set Frequency divisor which will drive the FPGA and analog mux selection
+	// Set Frequency divisor which will drive the FPGA and analog mux selection
 	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
 	SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
 	RELAY_OFF();
 
-// Disable modulation at default, which means enable the field
+	// Disable modulation at default, which means enable the field
 	LOW(GPIO_SSC_DOUT);
 
-// Give it a bit of time for the resonant antenna to settle.
+	// Give it a bit of time for the resonant antenna to settle.
 	SpinDelay(30);
 
-// Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
+	// Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
 	AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0);
 
-// Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the tag frames
+	// Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the tag frames
 	AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
 	AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;
 
-// Disable timer during configuration
+	// Disable timer during configuration
+	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
 	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
 
-// Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
+	// TC0: Capture mode, default timer source = MCK/2 (TIMER_CLOCK1), no triggers
-// external trigger rising edge, load RA on falling edge of TIOA.
+	AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK;
+
+	// TC1: Capture mode, default timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
+	// external trigger rising edge, load RA on falling edge of TIOA.
 	AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK
 			| AT91C_TC_ETRGEDG_FALLING | AT91C_TC_ABETRG
 			| AT91C_TC_LDRA_FALLING;
 
-// Enable and reset counters
+	// Enable and reset counters
 	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 
-// Reset the received frame, frame count and timing info
+	// Reset the received frame, frame count and timing info
 	frame_count = 0;
 	response = 0;
 	lastbit = 1;
@@ -2181,10 +2194,10 @@ void check_challenges_cmd(bool file_given, byte_t* data, uint64_t tagMode) {
 
 
 	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
-// Reset the return status
+	// Reset the return status
 	bSuccessful = false;
 
-// Clean up trace and prepare it for storing frames
+	// Clean up trace and prepare it for storing frames
 	set_tracing(true);
 	clear_trace();
 
@@ -2192,44 +2205,48 @@ void check_challenges_cmd(bool file_given, byte_t* data, uint64_t tagMode) {
 
 	LED_D_ON();
 
-// Configure output and enable pin that is connected to the FPGA (for modulating)
+	// Configure output and enable pin that is connected to the FPGA (for modulating)
 	AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
 	AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
 
-// Set fpga in edge detect with reader field, we can modulate as reader now
+	// Set fpga in edge detect with reader field, we can modulate as reader now
 	FpgaWriteConfWord(
 	FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
 
-// Set Frequency divisor which will drive the FPGA and analog mux selection
+	// Set Frequency divisor which will drive the FPGA and analog mux selection
 	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95);                  //125Khz
 	SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
 	RELAY_OFF();
 
-// Disable modulation at default, which means enable the field
+	// Disable modulation at default, which means enable the field
 	LOW(GPIO_SSC_DOUT);
 
-// Give it a bit of time for the resonant antenna to settle.
+	// Give it a bit of time for the resonant antenna to settle.
 	SpinDelay(30);
 
-// Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
+	// Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
 	AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0);
 
-// Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the tag frames
+	// Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the tag frames
 	AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
 	AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;
 
-// Disable timer during configuration
+	// Disable timer during configuration
+	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
 	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
 
-// Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
+	// TC0: Capture mode, default timer source = MCK/2 (TIMER_CLOCK1), no triggers
-// external trigger rising edge, load RA on falling edge of TIOA.
+	AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK;
+
+	// TC1: Capture mode, default timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
+	// external trigger rising edge, load RA on falling edge of TIOA.
 	AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK | AT91C_TC_ETRGEDG_FALLING | AT91C_TC_ABETRG | AT91C_TC_LDRA_FALLING;
 
-// Enable and reset counters
+	// Enable and reset counters
 	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 
-// Reset the received frame, frame count and timing info
+	// Reset the received frame, frame count and timing info
 	frame_count = 0;
 	response = 0;
 	lastbit = 1;

armsrc/hitagS.h

@@ -0,0 +1,26 @@
+//-----------------------------------------------------------------------------
+// This code is licensed to you under the terms of the GNU GPL, version 2 or,
+// at your option, any later version. See the LICENSE.txt file for the text of
+// the license.
+//-----------------------------------------------------------------------------
+// HitagS emulation (preliminary test version)
+//
+// (c) 2016 Oguzhan Cicek, Hendrik Schwartke, Ralf Spenneberg
+//     <info@os-s.de>
+//-----------------------------------------------------------------------------
+// Some code was copied from Hitag2.c
+//-----------------------------------------------------------------------------
+
+#ifndef HITAGS_H__
+#define HITAGS_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "hitag.h"
+
+void ReadHitagSCmd(hitag_function htf, hitag_data* htd, uint64_t startPage, uint64_t tagMode, bool readBlock);
+void SimulateHitagSTag(bool tag_mem_supplied, uint8_t* data);
+void WritePageHitagS(hitag_function htf, hitag_data* htd, int page);
+void check_challenges_cmd(bool file_given, uint8_t* data, uint64_t tagMode);
+
+#endif

client/cmdlfhitag.c

@@ -19,8 +19,7 @@
 #include "common.h"
 #include "util.h"
 #include "parity.h"
-#include "hitag2.h"
+#include "hitag.h"
-#include "hitagS.h"
 #include "cmdmain.h"
 
 static int CmdHelp(const char *Cmd);

include/hitag.h

@@ -0,0 +1,93 @@
+//-----------------------------------------------------------------------------
+// This code is licensed to you under the terms of the GNU GPL, version 2 or,
+// at your option, any later version. See the LICENSE.txt file for the text of
+// the license.
+//-----------------------------------------------------------------------------
+// Hitag2, HitagS
+//
+// (c) 2012 Roel Verdult
+// (c) 2016 Oguzhan Cicek, Hendrik Schwartke, Ralf Spenneberg
+//     <info@os-s.de>
+//-----------------------------------------------------------------------------
+
+
+#ifndef HITAG_H__
+#define HITAG_H__
+
+#ifdef _MSC_VER
+#define PACKED
+#else
+#define PACKED __attribute__((packed))
+#endif
+
+typedef enum {
+	RHTSF_CHALLENGE           = 01,
+	RHTSF_KEY                 = 02,
+	WHTSF_CHALLENGE           = 03,
+	WHTSF_KEY                 = 04,
+	RHT2F_PASSWORD            = 21,
+	RHT2F_AUTHENTICATE        = 22,
+	RHT2F_CRYPTO              = 23,
+	WHT2F_CRYPTO              = 24,
+	RHT2F_TEST_AUTH_ATTEMPTS  = 25,
+	RHT2F_UID_ONLY            = 26,
+} hitag_function;
+
+typedef struct {
+	uint8_t password[4];
+} PACKED rht2d_password;
+
+typedef struct {
+	uint8_t NrAr[8];
+	uint8_t data[4];
+} PACKED rht2d_authenticate;
+
+typedef struct {
+	uint8_t key[6];
+	uint8_t data[4];
+} PACKED rht2d_crypto;
+
+typedef union {
+	rht2d_password     pwd;
+	rht2d_authenticate auth;
+	rht2d_crypto       crypto;
+} hitag_data;
+
+
+//---------------------------------------------------------
+// Hitag S
+//---------------------------------------------------------
+typedef enum PROTO_STATE {READY=0,INIT,AUTHENTICATE,SELECTED,QUIET,TTF,FAIL} PSTATE;                                        //protocol-state
+typedef enum TAG_STATE   {NO_OP=0,READING_PAGE,READING_BLOCK,WRITING_PAGE_ACK,WRITING_PAGE_DATA,WRITING_BLOCK_DATA} TSATE;  //tag-state
+typedef enum SOF_TYPE    {STANDARD=0,ADVANCED,FAST_ADVANCED,ONE,NO_BITS} stype;                                             //number of start-of-frame bits
+
+struct hitagS_tag {
+	PSTATE   pstate;  //protocol-state
+	TSATE    tstate;  //tag-state
+	uint32_t uid;
+	uint8_t  pages[64][4];
+	uint64_t key;
+	uint8_t  pwdl0, pwdl1, pwdh0;
+	//con0
+	int      max_page;
+	stype    mode;
+	//con1
+	bool     auth;   //0=Plain 1=Auth
+	bool     TTFC;   //Transponder Talks first coding. 0=Manchester 1=Biphase
+	int      TTFDR;  //data rate in TTF Mode
+	int      TTFM;   //the number of pages that are sent to the RWD
+	bool     LCON;   //0=con1/2 read write 1=con1 read only and con2 OTP
+	bool     LKP;    //0=page2/3 read write 1=page2/3 read only in Plain mode and no access in authenticate mode
+	//con2
+	//0=read write 1=read only
+	bool     LCK7;   //page4/5
+	bool     LCK6;   //page6/7
+	bool     LCK5;   //page8-11
+	bool     LCK4;   //page12-15
+	bool     LCK3;   //page16-23
+	bool     LCK2;   //page24-31
+	bool     LCK1;   //page32-47
+	bool     LCK0;   //page48-63
+} ;
+
+#endif

include/hitag2.h

@@ -1,55 +0,0 @@
-//-----------------------------------------------------------------------------
-// (c) 2012 Roel Verdult
-//
-// This code is licensed to you under the terms of the GNU GPL, version 2 or,
-// at your option, any later version. See the LICENSE.txt file for the text of
-// the license.
-//-----------------------------------------------------------------------------
-// Hitag2 type prototyping
-//-----------------------------------------------------------------------------
-// HitagS added 
-//-----------------------------------------------------------------------------
-
-#ifndef _HITAG2_H_
-#define _HITAG2_H_
-
-#ifdef _MSC_VER
-#define PACKED
-#else
-#define PACKED __attribute__((packed))
-#endif
-
-typedef enum {
-	RHTSF_CHALLENGE           = 01,
-	RHTSF_KEY                 = 02,
-	WHTSF_CHALLENGE           = 03,
-	WHTSF_KEY                 = 04,
-	RHT2F_PASSWORD            = 21,
-	RHT2F_AUTHENTICATE        = 22,
-	RHT2F_CRYPTO              = 23,
-	WHT2F_CRYPTO              = 24,
-	RHT2F_TEST_AUTH_ATTEMPTS  = 25,
-	RHT2F_UID_ONLY            = 26,
-} hitag_function;
-
-typedef struct {
-	byte_t password[4];
-} PACKED rht2d_password;
-
-typedef struct {
-	byte_t NrAr[8];
-	byte_t data[4];
-} PACKED rht2d_authenticate;
-
-typedef struct {
-	byte_t key[6];
-	byte_t data[4];
-} PACKED rht2d_crypto;
-
-typedef union {
-	rht2d_password pwd;
-	rht2d_authenticate auth;
-	rht2d_crypto crypto;
-} hitag_data;
-
-#endif

include/hitagS.h

@@ -1,51 +0,0 @@
-//-----------------------------------------------------------------------------
-// This code is licensed to you under the terms of the GNU GPL, version 2 or,
-// at your option, any later version. See the LICENSE.txt file for the text of
-// the license.
-//-----------------------------------------------------------------------------
-// HitagS emulation (preliminary test version)
-//
-// (c) 2016 Oguzhan Cicek, Hendrik Schwartke, Ralf Spenneberg
-//     <info@os-s.de>
-//-----------------------------------------------------------------------------
-
-
-#ifndef _HITAGS_H_
-#define _HITAGS_H_
-
-#include "hitag2.h"
-
-typedef enum PROTO_STATE {READY=0,INIT,AUTHENTICATE,SELECTED,QUIET,TTF,FAIL} PSTATE;				//protocol-state
-typedef enum TAG_STATE   {NO_OP=0,READING_PAGE,READING_BLOCK,WRITING_PAGE_ACK,WRITING_PAGE_DATA,WRITING_BLOCK_DATA} TSATE;	//tag-state
-typedef enum SOF_TYPE    {STANDARD=0,ADVANCED,FAST_ADVANCED,ONE,NO_BITS} stype;					//number of start-of-frame bits
-
-struct hitagS_tag {
-	PSTATE pstate; //protocol-state
-	TSATE tstate;  //tag-state
-	uint32_t uid;
-	uint8_t  pages[64][4];
-	uint64_t key;
-	byte_t pwdl0,pwdl1,pwdh0;
-	//con0
-	int max_page;
-	stype mode;
-	//con1
-	bool auth;  //0=Plain 1=Auth
-	bool TTFC;  //Transponder Talks first coding. 0=Manchester 1=Biphase
-	int TTFDR;  //data rate in TTF Mode
-	int TTFM;   //the number of pages that are sent to the RWD
-	bool LCON;  //0=con1/2 read write 1=con1 read only and con2 OTP
-	bool LKP;   //0=page2/3 read write 1=page2/3 read only in Plain mode and no access in authenticate mode
-	//con2
-	//0=read write 1=read only
-	bool LCK7; //page4/5
-	bool LCK6; //page6/7
-	bool LCK5; //page8-11
-	bool LCK4; //page12-15
-	bool LCK3; //page16-23
-	bool LCK2; //page24-31
-	bool LCK1; //page32-47
-	bool LCK0; //page48-63
-} ;
-
-#endif