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revert removal of quarter frequency support for hi_read_rx_xcorr.v
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067bfc8b76
commit
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4 changed files with 20 additions and 16 deletions
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@ -58,6 +58,7 @@ void SetAdcMuxFor(uint32_t whichGpio);
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// Options for the HF reader, correlating against rx from tag
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// Options for the HF reader, correlating against rx from tag
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#define FPGA_HF_READER_RX_XCORR_848_KHZ (1<<0)
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#define FPGA_HF_READER_RX_XCORR_848_KHZ (1<<0)
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#define FPGA_HF_READER_RX_XCORR_SNOOP (1<<1)
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#define FPGA_HF_READER_RX_XCORR_SNOOP (1<<1)
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#define FPGA_HF_READER_RX_XCORR_QUARTER_FREQ (1<<2)
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// Options for the HF simulated tag, how to modulate
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// Options for the HF simulated tag, how to modulate
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#define FPGA_HF_SIMULATOR_NO_MODULATION (0<<0)
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#define FPGA_HF_SIMULATOR_NO_MODULATION (0<<0)
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#define FPGA_HF_SIMULATOR_MODULATE_BPSK (1<<0)
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#define FPGA_HF_SIMULATOR_MODULATE_BPSK (1<<0)
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BIN
fpga/fpga_hf.bit
BIN
fpga/fpga_hf.bit
Binary file not shown.
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@ -73,6 +73,8 @@ wire hi_read_tx_shallow_modulation = conf_word[0];
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wire hi_read_rx_xcorr_848 = conf_word[0];
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wire hi_read_rx_xcorr_848 = conf_word[0];
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// and whether to drive the coil (reader) or just short it (snooper)
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// and whether to drive the coil (reader) or just short it (snooper)
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wire hi_read_rx_xcorr_snoop = conf_word[1];
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wire hi_read_rx_xcorr_snoop = conf_word[1];
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// divide subcarrier frequency by 4
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wire hi_read_rx_xcorr_quarter = conf_word[2];
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// For the high-frequency simulated tag: what kind of modulation to use.
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// For the high-frequency simulated tag: what kind of modulation to use.
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wire [2:0] hi_simulate_mod_type = conf_word[2:0];
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wire [2:0] hi_simulate_mod_type = conf_word[2:0];
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@ -100,7 +102,7 @@ hi_read_rx_xcorr hrxc(
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hrxc_ssp_frame, hrxc_ssp_din, ssp_dout, hrxc_ssp_clk,
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hrxc_ssp_frame, hrxc_ssp_din, ssp_dout, hrxc_ssp_clk,
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cross_hi, cross_lo,
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cross_hi, cross_lo,
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hrxc_dbg,
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hrxc_dbg,
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hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop
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hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop, hi_read_rx_xcorr_quarter
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);
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);
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hi_simulate hs(
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hi_simulate hs(
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@ -10,7 +10,7 @@ module hi_read_rx_xcorr(
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ssp_frame, ssp_din, ssp_dout, ssp_clk,
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ssp_frame, ssp_din, ssp_dout, ssp_clk,
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cross_hi, cross_lo,
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cross_hi, cross_lo,
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dbg,
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dbg,
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xcorr_is_848, snoop
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xcorr_is_848, snoop, xcorr_quarter_freq
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);
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);
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input pck0, ck_1356meg, ck_1356megb;
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input pck0, ck_1356meg, ck_1356megb;
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output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
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output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
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@ -20,7 +20,7 @@ module hi_read_rx_xcorr(
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output ssp_frame, ssp_din, ssp_clk;
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output ssp_frame, ssp_din, ssp_clk;
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input cross_hi, cross_lo;
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input cross_hi, cross_lo;
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output dbg;
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output dbg;
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input xcorr_is_848, snoop;
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input xcorr_is_848, snoop, xcorr_quarter_freq;
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// Carrier is steady on through this, unless we're snooping.
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// Carrier is steady on through this, unless we're snooping.
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assign pwr_hi = ck_1356megb & (~snoop);
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assign pwr_hi = ck_1356megb & (~snoop);
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@ -28,19 +28,21 @@ assign pwr_oe1 = 1'b0;
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assign pwr_oe3 = 1'b0;
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assign pwr_oe3 = 1'b0;
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assign pwr_oe4 = 1'b0;
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assign pwr_oe4 = 1'b0;
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// Clock divider
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reg [2:0] fc_div;
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reg [0:0] fc_divider;
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always @(negedge ck_1356megb)
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always @(negedge ck_1356megb)
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fc_divider <= fc_divider + 1;
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fc_div <= fc_div + 1;
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wire fc_div2 = fc_divider[0];
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reg adc_clk;
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(* clock_signal = "yes" *) reg adc_clk; // sample frequency, always 16 * fc
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always @(ck_1356megb)
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always @(ck_1356megb, xcorr_is_848, xcorr_quarter_freq, fc_div)
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if (xcorr_is_848)
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if (xcorr_is_848 & ~xcorr_quarter_freq) // fc = 847.5 kHz
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adc_clk <= ck_1356megb;
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adc_clk <= ck_1356megb;
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else
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else if (~xcorr_is_848 & ~xcorr_quarter_freq) // fc = 424.25 kHz
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adc_clk <= fc_div2;
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adc_clk <= fc_div[0];
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else if (xcorr_is_848 & xcorr_quarter_freq) // fc = 212.125 kHz
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adc_clk <= fc_div[1];
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else // fc = 106.0625 kHz
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adc_clk <= fc_div[2];
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// When we're a reader, we just need to do the BPSK demod; but when we're an
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// When we're a reader, we just need to do the BPSK demod; but when we're an
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// eavesdropper, we also need to pick out the commands sent by the reader,
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// eavesdropper, we also need to pick out the commands sent by the reader,
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// using AM. Do this the same way that we do it for the simulated tag.
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// using AM. Do this the same way that we do it for the simulated tag.
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@ -71,8 +73,7 @@ end
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// so we need a 6-bit counter.
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// so we need a 6-bit counter.
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reg [5:0] corr_i_cnt;
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reg [5:0] corr_i_cnt;
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// And a couple of registers in which to accumulate the correlations.
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// And a couple of registers in which to accumulate the correlations.
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// we would add at most 32 times adc_d, the result can be held in 13 bits.
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// we would add/sub at most 32 times adc_d, the signed result can be held in 14 bits.
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// Need one additional bit because it can be negative as well
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reg signed [13:0] corr_i_accum;
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reg signed [13:0] corr_i_accum;
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reg signed [13:0] corr_q_accum;
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reg signed [13:0] corr_q_accum;
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reg signed [7:0] corr_i_out;
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reg signed [7:0] corr_i_out;
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@ -84,7 +85,7 @@ reg ssp_frame;
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always @(negedge adc_clk)
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always @(negedge adc_clk)
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begin
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begin
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corr_i_cnt <= corr_i_cnt + 1;
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corr_i_cnt <= corr_i_cnt + 1;
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end
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end
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