mirror of
https://github.com/Proxmark/proxmark3.git
synced 2025-08-20 13:23:25 -07:00
fix 'hf iclass sim'
* fix debug print on unhandled commands * deduplicate: use sim functions from iso15693.c * fix times in tracelog and 'hf list iclass' (sim only) * don't check parity in 'hf list iclass' * fix timing in TransmitTo15693Reader()
This commit is contained in:
pwpiwi
parent
0ab9002f36
commit
3d2c9c9b06
5 changed files with 204 additions and 327 deletions
254
armsrc/iclass.c
254
armsrc/iclass.c
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@ -42,9 +42,11 @@
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#include "apps.h"
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#include "util.h"
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#include "string.h"
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#include "printf.h"
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#include "common.h"
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#include "cmd.h"
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#include "iso14443a.h"
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#include "iso15693.h"
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// Needed for CRC in emulation mode;
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// same construction as in ISO 14443;
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// different initial value (CRC_ICLASS)
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@ -754,132 +756,7 @@ void rotateCSN(uint8_t* originalCSN, uint8_t* rotatedCSN) {
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}
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}
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//-----------------------------------------------------------------------------
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// Wait for commands from reader
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// Stop when button is pressed
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// Or return true when command is captured
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//-----------------------------------------------------------------------------
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static int GetIClassCommandFromReader(uint8_t *received, int *len, int maxLen) {
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// Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
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// only, since we are receiving, not transmitting).
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// Signal field is off with the appropriate LED
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LED_D_OFF();
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
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// Now run a `software UART' on the stream of incoming samples.
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Uart.output = received;
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Uart.byteCntMax = maxLen;
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Uart.state = STATE_UNSYNCD;
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for (;;) {
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WDT_HIT();
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if (BUTTON_PRESS()) return false;
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if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
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AT91C_BASE_SSC->SSC_THR = 0x00;
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}
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if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
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uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
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if (OutOfNDecoding(b & 0x0f)) {
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*len = Uart.byteCnt;
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return true;
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}
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}
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}
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}
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static uint8_t encode4Bits(const uint8_t b) {
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uint8_t c = b & 0xF;
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// OTA, the least significant bits first
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// The columns are
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// 1 - Bit value to send
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// 2 - Reversed (big-endian)
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// 3 - Manchester Encoded
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// 4 - Hex values
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switch(c){
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// 1 2 3 4
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case 15: return 0x55; // 1111 -> 1111 -> 01010101 -> 0x55
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case 14: return 0x95; // 1110 -> 0111 -> 10010101 -> 0x95
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case 13: return 0x65; // 1101 -> 1011 -> 01100101 -> 0x65
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case 12: return 0xa5; // 1100 -> 0011 -> 10100101 -> 0xa5
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case 11: return 0x59; // 1011 -> 1101 -> 01011001 -> 0x59
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case 10: return 0x99; // 1010 -> 0101 -> 10011001 -> 0x99
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case 9: return 0x69; // 1001 -> 1001 -> 01101001 -> 0x69
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case 8: return 0xa9; // 1000 -> 0001 -> 10101001 -> 0xa9
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case 7: return 0x56; // 0111 -> 1110 -> 01010110 -> 0x56
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case 6: return 0x96; // 0110 -> 0110 -> 10010110 -> 0x96
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case 5: return 0x66; // 0101 -> 1010 -> 01100110 -> 0x66
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case 4: return 0xa6; // 0100 -> 0010 -> 10100110 -> 0xa6
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case 3: return 0x5a; // 0011 -> 1100 -> 01011010 -> 0x5a
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case 2: return 0x9a; // 0010 -> 0100 -> 10011010 -> 0x9a
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case 1: return 0x6a; // 0001 -> 1000 -> 01101010 -> 0x6a
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default: return 0xaa; // 0000 -> 0000 -> 10101010 -> 0xaa
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}
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}
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//-----------------------------------------------------------------------------
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// Prepare tag messages
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//-----------------------------------------------------------------------------
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static void CodeIClassTagAnswer(const uint8_t *cmd, int len) {
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/*
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* SOF comprises 3 parts;
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* * An unmodulated time of 56.64 us
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* * 24 pulses of 423.75 kHz (fc/32)
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* * A logic 1, which starts with an unmodulated time of 18.88us
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* followed by 8 pulses of 423.75kHz (fc/32)
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*
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*
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* EOF comprises 3 parts:
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* - A logic 0 (which starts with 8 pulses of fc/32 followed by an unmodulated
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* time of 18.88us.
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* - 24 pulses of fc/32
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* - An unmodulated time of 56.64 us
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*
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*
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* A logic 0 starts with 8 pulses of fc/32
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* followed by an unmodulated time of 256/fc (~18,88us).
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*
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* A logic 0 starts with unmodulated time of 256/fc (~18,88us) followed by
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* 8 pulses of fc/32 (also 18.88us)
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*
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* The mode FPGA_HF_SIMULATOR_MODULATE_424K_8BIT which we use to simulate tag,
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* works like this.
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* - A 1-bit input to the FPGA becomes 8 pulses on 423.5kHz (fc/32) (18.88us).
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* - A 0-bit input to the FPGA becomes an unmodulated time of 18.88us
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*
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* In this mode the SOF can be written as 00011101 = 0x1D
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* The EOF can be written as 10111000 = 0xb8
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* A logic 1 is 01
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* A logic 0 is 10
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*
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* */
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int i;
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ToSendReset();
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// Send SOF
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ToSend[++ToSendMax] = 0x1D;
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for (i = 0; i < len; i++) {
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uint8_t b = cmd[i];
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ToSend[++ToSendMax] = encode4Bits(b & 0xF); // Least significant half
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ToSend[++ToSendMax] = encode4Bits((b >>4) & 0xF); // Most significant half
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}
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// Send EOF
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ToSend[++ToSendMax] = 0xB8;
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//lastProxToAirDuration = 8*ToSendMax - 3*8 - 3*8;//Not counting zeroes in the beginning or end
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// Convert from last byte pos to length
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ToSendMax++;
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}
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// Only SOF
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// Encode SOF only
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static void CodeIClassTagSOF() {
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//So far a dummy implementation, not used
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//int lastProxToAirDuration =0;
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@ -897,43 +774,6 @@ static void AppendCrc(uint8_t *data, int len) {
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ComputeCrc14443(CRC_ICLASS, data, len, data+len, data+len+1);
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}
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static int SendIClassAnswer(uint8_t *resp, int respLen, int delay) {
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int i = 0, d = 0;//, u = 0, d = 0;
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uint8_t b = 0;
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//FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR|FPGA_HF_SIMULATOR_MODULATE_424K);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_424K_8BIT);
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AT91C_BASE_SSC->SSC_THR = 0x00;
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FpgaSetupSsc(FPGA_MAJOR_MODE_HF_SIMULATOR);
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while (true) {
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if ((AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY)){
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b = AT91C_BASE_SSC->SSC_RHR;
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(void) b;
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}
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if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)){
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b = 0x00;
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if (d < delay) {
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// send 0x00 byte (causing a 2048/13,56MHz = 151us delay)
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d++;
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} else {
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if (i < respLen) {
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b = resp[i];
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}
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i++;
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}
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AT91C_BASE_SSC->SSC_THR = b;
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}
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// if (i > respLen +4) break;
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if (i > respLen + 1) break;
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// send 2 more 0x00 bytes (causing a 302us delay)
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}
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return 0;
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}
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/**
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* @brief Does the actual simulation
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@ -1032,33 +872,33 @@ int doIClassSimulation(int simulationMode, uint8_t *reader_mac_buf) {
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// Prepare card messages
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ToSendMax = 0;
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// First card answer: SOF
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// First card answer: SOF only
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CodeIClassTagSOF();
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memcpy(resp_sof, ToSend, ToSendMax);
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resp_sof_Len = ToSendMax;
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// Anticollision CSN
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CodeIClassTagAnswer(anticoll_data, sizeof(anticoll_data));
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CodeIso15693AsTag(anticoll_data, sizeof(anticoll_data));
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memcpy(resp_anticoll, ToSend, ToSendMax);
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resp_anticoll_len = ToSendMax;
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// CSN (block 0)
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CodeIClassTagAnswer(csn_data, sizeof(csn_data));
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CodeIso15693AsTag(csn_data, sizeof(csn_data));
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memcpy(resp_csn, ToSend, ToSendMax);
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resp_csn_len = ToSendMax;
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// Configuration (block 1)
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CodeIClassTagAnswer(conf_data, sizeof(conf_data));
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CodeIso15693AsTag(conf_data, sizeof(conf_data));
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memcpy(resp_conf, ToSend, ToSendMax);
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resp_conf_len = ToSendMax;
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// e-Purse (block 2)
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CodeIClassTagAnswer(card_challenge_data, sizeof(card_challenge_data));
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CodeIso15693AsTag(card_challenge_data, sizeof(card_challenge_data));
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memcpy(resp_cc, ToSend, ToSendMax);
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resp_cc_len = ToSendMax;
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// Application Issuer Area (block 5)
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CodeIClassTagAnswer(aia_data, sizeof(aia_data));
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CodeIso15693AsTag(aia_data, sizeof(aia_data));
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memcpy(resp_aia, ToSend, ToSendMax);
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resp_aia_len = ToSendMax;
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@ -1066,33 +906,22 @@ int doIClassSimulation(int simulationMode, uint8_t *reader_mac_buf) {
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uint8_t *data_generic_trace = BigBuf_malloc(8 + 2); // 8 bytes data + 2byte CRC is max tag answer
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uint8_t *data_response = BigBuf_malloc( (8 + 2) * 2 + 2);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
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SpinDelay(100);
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StartCountSspClk();
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// We need to listen to the high-frequency, peak-detected path.
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SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
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FpgaSetupSsc(FPGA_MAJOR_MODE_HF_ISO14443A);
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uint32_t time_0 = GetCountSspClk();
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uint32_t t2r_time =0;
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uint32_t r2t_time =0;
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LED_A_ON();
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bool buttonPressed = false;
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uint8_t response_delay = 1;
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while (!exitLoop) {
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WDT_HIT();
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response_delay = 1;
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LED_B_OFF();
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//Signal tracer
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// Can be used to get a trigger for an oscilloscope..
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LED_C_OFF();
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if (!GetIClassCommandFromReader(receivedCmd, &len, 100)) {
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uint32_t reader_eof_time = 0;
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len = GetIso15693CommandFromReader(receivedCmd, MAX_FRAME_SIZE, &reader_eof_time);
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if (len < 0) {
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buttonPressed = true;
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break;
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}
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r2t_time = GetCountSspClk();
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//Signal tracer
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LED_C_ON();
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@ -1116,7 +945,7 @@ int doIClassSimulation(int simulationMode, uint8_t *reader_mac_buf) {
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trace_data = anticoll_data;
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trace_data_size = sizeof(anticoll_data);
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//DbpString("Reader requests anticollission CSN:");
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} else if (receivedCmd[0] == ICLASS_CMD_READ_OR_IDENTIFY && len == 4) { // read block
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uint16_t blockNo = receivedCmd[1];
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if (simulationMode != ICLASS_SIM_MODE_FULL) {
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@ -1157,7 +986,7 @@ int doIClassSimulation(int simulationMode, uint8_t *reader_mac_buf) {
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AppendCrc(data_generic_trace, 8);
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trace_data = data_generic_trace;
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trace_data_size = 10;
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CodeIClassTagAnswer(trace_data, trace_data_size);
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CodeIso15693AsTag(trace_data, trace_data_size);
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memcpy(data_response, ToSend, ToSendMax);
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modulated_response = data_response;
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modulated_response_size = ToSendMax;
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@ -1183,26 +1012,18 @@ int doIClassSimulation(int simulationMode, uint8_t *reader_mac_buf) {
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} else if (receivedCmd[0] == ICLASS_CMD_CHECK) {
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// Reader random and reader MAC!!!
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if (simulationMode == ICLASS_SIM_MODE_FULL) {
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//NR, from reader, is in receivedCmd +1
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//NR, from reader, is in receivedCmd+1
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opt_doTagMAC_2(cipher_state, receivedCmd+1, data_generic_trace, diversified_key);
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trace_data = data_generic_trace;
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trace_data_size = 4;
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CodeIClassTagAnswer(trace_data, trace_data_size);
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CodeIso15693AsTag(trace_data, trace_data_size);
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memcpy(data_response, ToSend, ToSendMax);
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modulated_response = data_response;
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modulated_response_size = ToSendMax;
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response_delay = 0; //We need to hurry here... (but maybe not too much... ??)
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//exitLoop = true;
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} else { // Not fullsim, we don't respond
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// We do not know what to answer, so lets keep quiet
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if (simulationMode == ICLASS_SIM_MODE_EXIT_AFTER_MAC) {
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// dbprintf:ing ...
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Dbprintf("CSN: %02x %02x %02x %02x %02x %02x %02x %02x"
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,csn[0],csn[1],csn[2],csn[3],csn[4],csn[5],csn[6],csn[7]);
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Dbprintf("RDR: (len=%02d): %02x %02x %02x %02x %02x %02x %02x %02x %02x",len,
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receivedCmd[0], receivedCmd[1], receivedCmd[2],
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receivedCmd[3], receivedCmd[4], receivedCmd[5],
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receivedCmd[6], receivedCmd[7], receivedCmd[8]);
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if (reader_mac_buf != NULL) {
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// save NR and MAC for sim 2,4
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memcpy(reader_mac_buf + 8, receivedCmd + 1, 8);
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@ -1223,14 +1044,11 @@ int doIClassSimulation(int simulationMode, uint8_t *reader_mac_buf) {
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// OBS! If this is implemented, don't forget to regenerate the cipher_state
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// We're expected to respond with the data+crc, exactly what's already in the receivedCmd
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// receivedCmd is now UPDATE 1b | ADDRESS 1b | DATA 8b | Signature 4b or CRC 2b
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//Take the data...
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memcpy(data_generic_trace, receivedCmd + 2, 8);
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//Add crc
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AppendCrc(data_generic_trace, 8);
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trace_data = data_generic_trace;
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trace_data_size = 10;
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CodeIClassTagAnswer(trace_data, trace_data_size);
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CodeIso15693AsTag(trace_data, trace_data_size);
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memcpy(data_response, ToSend, ToSendMax);
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modulated_response = data_response;
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modulated_response_size = ToSendMax;
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@ -1243,9 +1061,13 @@ int doIClassSimulation(int simulationMode, uint8_t *reader_mac_buf) {
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// Otherwise, we should answer 8bytes (block) + 2bytes CRC
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} else {
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//#db# Unknown command received from reader (len=5): 26 1 0 f6 a 44 44 44 44
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// Never seen this command before
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print_result("Unhandled command received from reader ", receivedCmd, len);
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char debug_message[250]; // should be enough
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sprintf(debug_message, "Unhandled command (len = %d) received from reader:", len);
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for (int i = 0; i < len && strlen(debug_message) < sizeof(debug_message) - 3 - 1; i++) {
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sprintf(debug_message + strlen(debug_message), " %02x", receivedCmd[i]);
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}
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Dbprintf("%s", debug_message);
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// Do not respond
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}
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@ -1253,22 +1075,11 @@ int doIClassSimulation(int simulationMode, uint8_t *reader_mac_buf) {
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A legit tag has about 330us delay between reader EOT and tag SOF.
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**/
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if (modulated_response_size > 0) {
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SendIClassAnswer(modulated_response, modulated_response_size, response_delay);
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t2r_time = GetCountSspClk();
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uint32_t response_time = reader_eof_time + DELAY_ISO15693_VCD_TO_VICC_SIM - DELAY_ARM_TO_READER_SIM;
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TransmitTo15693Reader(modulated_response, modulated_response_size, response_time, false);
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LogTrace(trace_data, trace_data_size, response_time + DELAY_ARM_TO_READER_SIM, response_time + (modulated_response_size << 6) + DELAY_ARM_TO_READER_SIM, NULL, false);
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}
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uint8_t parity[MAX_PARITY_SIZE];
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GetParity(receivedCmd, len, parity);
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LogTrace(receivedCmd, len, (r2t_time-time_0) << 4, (r2t_time-time_0) << 4, parity, true);
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if (trace_data != NULL) {
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GetParity(trace_data, trace_data_size, parity);
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LogTrace(trace_data, trace_data_size, (t2r_time-time_0) << 4, (t2r_time-time_0) << 4, parity, false);
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}
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if (!get_tracing()) {
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DbpString("Trace full");
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//break;
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}
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}
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LED_A_OFF();
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@ -1298,7 +1109,12 @@ void SimulateIClass(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain
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uint32_t simType = arg0;
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uint32_t numberOfCSNS = arg1;
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// setup hardware for simulation:
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FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
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SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_NO_MODULATION);
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FpgaSetupSsc(FPGA_MAJOR_MODE_HF_SIMULATOR);
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StartCountSspClk();
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// Enable and clear the trace
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set_tracing(true);
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@ -1330,6 +1146,12 @@ void SimulateIClass(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain
|
|||
// Button pressed
|
||||
break;
|
||||
}
|
||||
Dbprintf("CSN: %02x %02x %02x %02x %02x %02x %02x %02x",
|
||||
datain[i*8+0], datain[i*8+1], datain[i*8+2], datain[i*8+3],
|
||||
datain[i*8+4], datain[i*8+5], datain[i*8+6], datain[i*8+7]);
|
||||
Dbprintf("NR,MAC: %02x %02x %02x %02x %02x %02x %02x %02x",
|
||||
datain[i*8+ 8], datain[i*8+ 9], datain[i*8+10], datain[i*8+11],
|
||||
datain[i*8+12], datain[i*8+13], datain[i*8+14], datain[i*8+15]);
|
||||
}
|
||||
cmd_send(CMD_ACK, CMD_SIMULATE_TAG_ICLASS, i, 0, mac_responses, i*16);
|
||||
} else if (simType == ICLASS_SIM_MODE_FULL) {
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue