mirror of
https://github.com/Proxmark/proxmark3.git
synced 2025-08-19 21:03:23 -07:00
Added LF frequency adjustments from d18c7db, cleaned up code,
typo fixes in iso14443a code, added the missing "tools" directory, added initial elements for online/offline detection for commands.
This commit is contained in:
edouard@lafargue.name
parent
974ba9a205
commit
30f2a7d38f
16 changed files with 10914 additions and 161 deletions
25
fpga/fpga.v
25
fpga/fpga.v
|
|
@ -21,7 +21,7 @@
|
|||
`include "util.v"
|
||||
|
||||
module fpga(
|
||||
spck, miso, mosi, ncs,
|
||||
spcki, miso, mosi, ncs,
|
||||
pck0i, ck_1356meg, ck_1356megb,
|
||||
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
|
||||
adc_d, adc_clk, adc_noe,
|
||||
|
|
@ -29,7 +29,7 @@ module fpga(
|
|||
cross_hi, cross_lo,
|
||||
dbg
|
||||
);
|
||||
input spck, mosi, ncs;
|
||||
input spcki, mosi, ncs;
|
||||
output miso;
|
||||
input pck0i, ck_1356meg, ck_1356megb;
|
||||
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
|
||||
|
|
@ -40,11 +40,16 @@ module fpga(
|
|||
input cross_hi, cross_lo;
|
||||
output dbg;
|
||||
|
||||
//assign pck0 = pck0i;
|
||||
IBUFG #(.IOSTANDARD("DEFAULT") ) pck0b(
|
||||
.O(pck0),
|
||||
.I(pck0i)
|
||||
);
|
||||
//assign pck0 = pck0i;
|
||||
//assign spck = spcki;
|
||||
IBUFG #(.IOSTANDARD("DEFAULT") ) spckb(
|
||||
.O(spck),
|
||||
.I(spcki)
|
||||
);
|
||||
//-----------------------------------------------------------------------------
|
||||
// The SPI receiver. This sets up the configuration word, which the rest of
|
||||
// the logic looks at to determine how to connect the A/D and the coil
|
||||
|
|
@ -52,7 +57,8 @@ module fpga(
|
|||
// to the configuration bits, for use below.
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
reg [7:0] conf_word_shift;
|
||||
reg [15:0] shift_reg;
|
||||
reg [7:0] divisor;
|
||||
reg [7:0] conf_word;
|
||||
|
||||
// We switch modes between transmitting to the 13.56 MHz tag and receiving
|
||||
|
|
@ -60,15 +66,18 @@ reg [7:0] conf_word;
|
|||
// glitching, or else we will glitch the transmitted carrier.
|
||||
always @(posedge ncs)
|
||||
begin
|
||||
conf_word <= conf_word_shift;
|
||||
case(shift_reg[15:12])
|
||||
4'b0001: conf_word <= shift_reg[7:0];
|
||||
4'b0010: divisor <= shift_reg[7:0];
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge spck)
|
||||
begin
|
||||
if(~ncs)
|
||||
begin
|
||||
conf_word_shift[7:1] <= conf_word_shift[6:0];
|
||||
conf_word_shift[0] <= mosi;
|
||||
shift_reg[15:1] <= shift_reg[14:0];
|
||||
shift_reg[0] <= mosi;
|
||||
end
|
||||
end
|
||||
|
||||
|
|
@ -110,7 +119,7 @@ lo_read lr(
|
|||
lr_ssp_frame, lr_ssp_din, ssp_dout, lr_ssp_clk,
|
||||
cross_hi, cross_lo,
|
||||
lr_dbg,
|
||||
lo_is_125khz
|
||||
lo_is_125khz, divisor
|
||||
);
|
||||
|
||||
lo_simulate ls(
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
//-----------------------------------------------------------------------------
|
||||
// The way that we connect things in low-frequency read mode. In this case
|
||||
// we are generating the 134 kHz or 125 kHz carrier, and running the
|
||||
// we are generating the 134 kHz or 125 kHz carrier, and running the
|
||||
// unmodulated carrier at that frequency. The A/D samples at that same rate,
|
||||
// and the result is serialized.
|
||||
//
|
||||
|
|
@ -14,7 +14,7 @@ module lo_read(
|
|||
ssp_frame, ssp_din, ssp_dout, ssp_clk,
|
||||
cross_hi, cross_lo,
|
||||
dbg,
|
||||
lo_is_125khz
|
||||
lo_is_125khz, divisor
|
||||
);
|
||||
input pck0, ck_1356meg, ck_1356megb;
|
||||
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
|
||||
|
|
@ -25,6 +25,7 @@ module lo_read(
|
|||
input cross_hi, cross_lo;
|
||||
output dbg;
|
||||
input lo_is_125khz;
|
||||
input [7:0] divisor;
|
||||
|
||||
// The low-frequency RFID stuff. This is relatively simple, because most
|
||||
// of the work happens on the ARM, and we just pass samples through. The
|
||||
|
|
@ -38,65 +39,39 @@ module lo_read(
|
|||
// 125 kHz by dividing by a further factor of (8*12*2), or ~134 kHz by
|
||||
// dividing by a factor of (8*11*2) (for 136 kHz, ~2% error, tolerable).
|
||||
|
||||
reg [3:0] pck_divider;
|
||||
reg clk_lo;
|
||||
reg [7:0] to_arm_shiftreg;
|
||||
reg [7:0] pck_divider;
|
||||
reg [6:0] ssp_divider;
|
||||
reg ant_lo;
|
||||
|
||||
always @(posedge pck0)
|
||||
begin
|
||||
if(lo_is_125khz)
|
||||
begin
|
||||
if(pck_divider == 4'd11)
|
||||
begin
|
||||
pck_divider <= 4'd0;
|
||||
clk_lo = !clk_lo;
|
||||
end
|
||||
else
|
||||
pck_divider <= pck_divider + 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if(pck_divider == 4'd10)
|
||||
begin
|
||||
pck_divider <= 4'd0;
|
||||
clk_lo = !clk_lo;
|
||||
end
|
||||
else
|
||||
pck_divider <= pck_divider + 1;
|
||||
end
|
||||
if(pck_divider == 8'd0)
|
||||
begin
|
||||
pck_divider <= divisor[7:0];
|
||||
ant_lo = !ant_lo;
|
||||
if(ant_lo == 1'b0)
|
||||
begin
|
||||
ssp_divider <= 7'b0011111;
|
||||
to_arm_shiftreg <= adc_d;
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
pck_divider <= pck_divider - 1;
|
||||
if(ssp_divider[6] == 1'b0)
|
||||
begin
|
||||
if (ssp_divider[1:0] == 1'b11) to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];
|
||||
ssp_divider <= ssp_divider - 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg [2:0] carrier_divider_lo;
|
||||
|
||||
always @(posedge clk_lo)
|
||||
begin
|
||||
carrier_divider_lo <= carrier_divider_lo + 1;
|
||||
end
|
||||
|
||||
assign pwr_lo = carrier_divider_lo[2];
|
||||
|
||||
// This serializes the values returned from the A/D, and sends them out
|
||||
// over the SSP.
|
||||
|
||||
reg [7:0] to_arm_shiftreg;
|
||||
|
||||
always @(posedge clk_lo)
|
||||
begin
|
||||
if(carrier_divider_lo == 3'b000)
|
||||
to_arm_shiftreg <= adc_d;
|
||||
else
|
||||
to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];
|
||||
end
|
||||
|
||||
assign ssp_clk = clk_lo;
|
||||
assign ssp_frame = (carrier_divider_lo == 3'b001);
|
||||
assign ssp_din = to_arm_shiftreg[7];
|
||||
|
||||
// The ADC converts on the falling edge, and our serializer loads when
|
||||
// carrier_divider_lo == 3'b000.
|
||||
assign adc_clk = ~carrier_divider_lo[2];
|
||||
|
||||
assign ssp_clk = pck_divider[1];
|
||||
assign ssp_frame = ~ssp_divider[5];
|
||||
assign pwr_hi = 1'b0;
|
||||
|
||||
assign pwr_lo = ant_lo;
|
||||
assign adc_clk = ~ant_lo;
|
||||
assign dbg = adc_clk;
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
`include "lo_read_org.v"
|
||||
`include "lo_read.v"
|
||||
|
||||
/*
|
||||
pck0 - input main 24Mhz clock (PLL / 4)
|
||||
[7:0] adc_d - input data from A/D converter
|
||||
|
|
@ -29,6 +29,7 @@ module testbed_lo_read;
|
|||
reg pck0;
|
||||
reg [7:0] adc_d;
|
||||
reg lo_is_125khz;
|
||||
reg [15:0] divisor;
|
||||
|
||||
wire pwr_lo;
|
||||
wire adc_clk;
|
||||
|
|
@ -47,38 +48,61 @@ module testbed_lo_read;
|
|||
wire cross_hi;
|
||||
wire dbg;
|
||||
|
||||
lo_read #(5,200) dut(
|
||||
lo_read_org #(5,10) dut1(
|
||||
.pck0(pck0),
|
||||
.ck_1356meg(ck_1356meg),
|
||||
.ck_1356megb(ck_1356megb),
|
||||
.pwr_lo(pwr_lo),
|
||||
.pwr_hi(pwr_hi),
|
||||
.pwr_oe1(pwr_oe1),
|
||||
.pwr_oe2(pwr_oe2),
|
||||
.pwr_oe3(pwr_oe3),
|
||||
.pwr_oe4(pwr_oe4),
|
||||
.ck_1356meg(ack_1356meg),
|
||||
.ck_1356megb(ack_1356megb),
|
||||
.pwr_lo(apwr_lo),
|
||||
.pwr_hi(apwr_hi),
|
||||
.pwr_oe1(apwr_oe1),
|
||||
.pwr_oe2(apwr_oe2),
|
||||
.pwr_oe3(apwr_oe3),
|
||||
.pwr_oe4(apwr_oe4),
|
||||
.adc_d(adc_d),
|
||||
.adc_clk(adc_clk),
|
||||
.ssp_frame(ssp_frame),
|
||||
.ssp_din(ssp_din),
|
||||
.ssp_dout(ssp_dout),
|
||||
.ssp_clk(ssp_clk),
|
||||
.cross_hi(cross_hi),
|
||||
.cross_lo(cross_lo),
|
||||
.dbg(dbg),
|
||||
.ssp_frame(assp_frame),
|
||||
.ssp_din(assp_din),
|
||||
.ssp_dout(assp_dout),
|
||||
.ssp_clk(assp_clk),
|
||||
.cross_hi(across_hi),
|
||||
.cross_lo(across_lo),
|
||||
.dbg(adbg),
|
||||
.lo_is_125khz(lo_is_125khz)
|
||||
);
|
||||
|
||||
integer idx, i;
|
||||
lo_read #(5,10) dut2(
|
||||
.pck0(pck0),
|
||||
.ck_1356meg(bck_1356meg),
|
||||
.ck_1356megb(bck_1356megb),
|
||||
.pwr_lo(bpwr_lo),
|
||||
.pwr_hi(bpwr_hi),
|
||||
.pwr_oe1(bpwr_oe1),
|
||||
.pwr_oe2(bpwr_oe2),
|
||||
.pwr_oe3(bpwr_oe3),
|
||||
.pwr_oe4(bpwr_oe4),
|
||||
.adc_d(adc_d),
|
||||
.adc_clk(badc_clk),
|
||||
.ssp_frame(bssp_frame),
|
||||
.ssp_din(bssp_din),
|
||||
.ssp_dout(bssp_dout),
|
||||
.ssp_clk(bssp_clk),
|
||||
.cross_hi(bcross_hi),
|
||||
.cross_lo(bcross_lo),
|
||||
.dbg(bdbg),
|
||||
.lo_is_125khz(lo_is_125khz),
|
||||
.divisor(divisor)
|
||||
);
|
||||
|
||||
integer idx, i, adc_val=8;
|
||||
|
||||
// main clock
|
||||
always #5 pck0 = !pck0;
|
||||
|
||||
//new A/D value available from ADC on positive edge
|
||||
task crank_dut;
|
||||
begin
|
||||
@(posedge adc_clk) ;
|
||||
adc_d = $random;
|
||||
adc_d = adc_val;
|
||||
adc_val = (adc_val *2) + 53;
|
||||
end
|
||||
endtask
|
||||
|
||||
|
|
@ -87,19 +111,13 @@ module testbed_lo_read;
|
|||
// init inputs
|
||||
pck0 = 0;
|
||||
adc_d = 0;
|
||||
|
||||
// simulate 4 A/D cycles at 134Khz
|
||||
lo_is_125khz=0;
|
||||
for (i = 0 ; i < 4 ; i = i + 1) begin
|
||||
crank_dut;
|
||||
end
|
||||
lo_is_125khz = 1;
|
||||
divisor=255; //min 19, 95=125Khz, max 255
|
||||
|
||||
// simulate 4 A/D cycles at 125Khz
|
||||
lo_is_125khz=1;
|
||||
for (i = 0 ; i < 4 ; i = i + 1) begin
|
||||
for (i = 0 ; i < 8 ; i = i + 1) begin
|
||||
crank_dut;
|
||||
end
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule // main
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue