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Added LF frequency adjustments from d18c7db, cleaned up code,

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typo fixes in iso14443a code, added the missing "tools" directory,
added initial elements for online/offline detection for commands.
This commit is contained in:
edouard@lafargue.name 2009-04-15 08:09:06 +00:00
commit 30f2a7d38f
16 changed files with 10914 additions and 161 deletions
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49
armsrc/appmain.c
View file

@ -87,8 +87,10 @@ void AcquireRawAdcSamples125k(BOOL at134khz)
memset(dest,0,n);
if(at134khz) {
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_134_KHZ);
} else {
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_125_KHZ);
}
@ -121,7 +123,7 @@ void AcquireRawAdcSamples125k(BOOL at134khz)
//-----------------------------------------------------------------------------
// Read an ADC channel and block till it completes, then return the result
// in ADC units (0 to 1023). Also a routine to average sixteen samples and
// in ADC units (0 to 1023). Also a routine to average 32 samples and
// return that.
//-----------------------------------------------------------------------------
static int ReadAdc(int ch)
@ -152,6 +154,29 @@ static int AvgAdc(int ch)
return (a + 15) >> 5;
}
/*
* Sweeps the useful LF range of the proxmark from
* 46.8kHz (divisor=255) to 600kHz (divisor=19) and
* reads the voltage in the antenna: the result is a graph
* which should clearly show the resonating frequency of your
* LF antenna ( hopefully around 90 if it is tuned to 125kHz!)
*/
void SweepLFrange()
{
BYTE *dest = (BYTE *)BigBuf;
int i;
// clear buffer
memset(BigBuf,0,sizeof(BigBuf));
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
for (i=255; i>19; i--) {
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, i);
SpinDelay(20);
dest[i] = (137500 * AvgAdc(4)) >> 18;
}
}
void MeasureAntennaTuning(void)
{
@ -164,6 +189,7 @@ void MeasureAntennaTuning(void)
UsbCommand c;
// Let the FPGA drive the low-frequency antenna around 125 kHz.
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_125_KHZ);
SpinDelay(20);
vLf125 = AvgAdc(4);
@ -172,6 +198,7 @@ void MeasureAntennaTuning(void)
vLf125 = (137500 * vLf125) >> 10;
// Let the FPGA drive the low-frequency antenna around 134 kHz.
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_134_KHZ);
SpinDelay(20);
vLf134 = AvgAdc(4);
@ -207,7 +234,7 @@ void SimulateTagLowFrequency(int period)
PIO_OUTPUT_DISABLE = (1 << GPIO_SSC_CLK);
#define SHORT_COIL() LOW(GPIO_SSC_DOUT)
#define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
#define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
i = 0;
for(;;) {
@ -345,6 +372,7 @@ static void CmdHIDdemodFSK(void)
int m=0, n=0, i=0, idx=0, found=0, lastval=0;
DWORD hi=0, lo=0;
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_125_KHZ);
// Connect the A/D to the peak-detected low-frequency path.
@ -448,7 +476,7 @@ static void CmdHIDdemodFSK(void)
dest[i++]=dest[idx-1];
dest[i++]=dest[idx-1];
break;
// When a logic 0 is immediately followed by the start of the next transmisson
// When a logic 0 is immediately followed by the start of the next transmisson
// (special pattern) a pattern of 4 bit duration lengths is created.
case 4:
dest[i++]=dest[idx-1];
@ -573,20 +601,19 @@ void UsbPacketReceived(BYTE *packet, int len)
break;
case CMD_READER_ISO_15693:
ReaderIso15693(c->ext1);
ReaderIso15693(c->ext1);
break;
case CMD_SIMTAG_ISO_15693:
SimTagIso15693(c->ext1);
SimTagIso15693(c->ext1);
break;
case CMD_ACQUIRE_RAW_ADC_SAMPLES_ISO_14443:
AcquireRawAdcSamplesIso14443(c->ext1);
break;
case CMD_READER_ISO_14443a:
ReaderIso14443a(c->ext1);
ReaderIso14443a(c->ext1);
break;
case CMD_SNOOP_ISO_14443:
@ -656,6 +683,14 @@ void UsbPacketReceived(BYTE *packet, int len)
LCDReset();
break;
case CMD_SWEEP_LF:
SweepLFrange();
break;
case CMD_SET_LF_DIVISOR:
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, c->ext1);
break;
case CMD_LCD:
LCDSend(c->ext1);
break;

4
armsrc/apps.h
View file

@ -19,6 +19,7 @@ extern BYTE ToSend[];
extern DWORD BigBuf[];
/// fpga.c
void FpgaSendCommand(WORD cmd, WORD v);
void FpgaWriteConfWord(BYTE v);
void FpgaDownloadAndGo(void);
void FpgaSetupSsc(void);
@ -26,6 +27,9 @@ void SetupSpi(int mode);
void FpgaSetupSscDma(BYTE *buf, int len);
void SetAdcMuxFor(int whichGpio);
// Definitions for the FPGA commands.
#define FPGA_CMD_SET_CONFREG (1<<12)
#define FPGA_CMD_SET_DIVISOR (2<<12)
// Definitions for the FPGA configuration word.
#define FPGA_MAJOR_MODE_LF_READER (0<<5)
#define FPGA_MAJOR_MODE_LF_SIMULATOR (1<<5)

20
armsrc/fpga.c
View file

@ -53,7 +53,7 @@ void SetupSpi(int mode)
( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)
( 1 << 16) | // Delay Before SPCK (1 MCK period)
( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
( 0 << 4) | // Bits per Transfer (8 bits)
( 8 << 4) | // Bits per Transfer (16 bits)
( 0 << 3) | // Chip Select inactive after transfer
( 1 << 1) | // Clock Phase data captured on leading edge, changes on following edge
( 0 << 0); // Clock Polarity inactive state is logic 0
@ -185,15 +185,25 @@ void FpgaDownloadAndGo(void)
LED_D_OFF();
}
//-----------------------------------------------------------------------------
// Send a 16 bit command/data pair to the FPGA.
// The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
// where C is the 4 bit command and D is the 12 bit data
//-----------------------------------------------------------------------------
void FpgaSendCommand(WORD cmd, WORD v)
{
SetupSpi(SPI_FPGA_MODE);
while ((SPI_STATUS & SPI_STATUS_TX_EMPTY) == 0); // wait for the transfer to complete
SPI_TX_DATA = SPI_CONTROL_LAST_TRANSFER | cmd | v; // send the data
}
//-----------------------------------------------------------------------------
// Write the FPGA setup word (that determines what mode the logic is in, read
// vs. clone vs. etc.).
// vs. clone vs. etc.). This is now a special case of FpgaSendCommand() to
// avoid changing this function's occurence everywhere in the source code.
//-----------------------------------------------------------------------------
void FpgaWriteConfWord(BYTE v)
{
SetupSpi(SPI_FPGA_MODE);
while ((SPI_STATUS & SPI_STATUS_TX_EMPTY) == 0); // wait for the transfer to complete
SPI_TX_DATA = SPI_CONTROL_LAST_TRANSFER | v; // send the data
FpgaSendCommand(FPGA_CMD_SET_CONFREG, v);
}
//-----------------------------------------------------------------------------

10541
armsrc/fpgaimg.c
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File diff suppressed because it is too large Load diff

2
armsrc/iso14443.c
View file

@ -6,7 +6,7 @@
//-----------------------------------------------------------------------------
#include <proxmark3.h>
#include "apps.h"
#include "..\common\iso14443_crc.c"
#include "../common/iso14443_crc.c"
//static void GetSamplesFor14443(BOOL weTx, int n);

4
armsrc/iso14443a.c
View file

@ -5,7 +5,7 @@
//-----------------------------------------------------------------------------
#include <proxmark3.h>
#include "apps.h"
#include "..\common\iso14443_crc.c"
#include "../common/iso14443_crc.c"
typedef enum {
SEC_D = 1,
@ -1686,7 +1686,7 @@ void ReaderIso14443a(DWORD parameter)
// OK we have selected at least at cascade 1, lets see if first byte of UID was 0x88 in
// which case we need to make a cascade 2 request and select - this is a long UID
if (receivedAnswer[0] = 0x88)
if (receivedAnswer[0] == 0x88)
{
// Do cascade level 2 stuff
///////////////////////////////////////////////////////////////////