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Updated logic in lo_read.v so it's much tidier now, better timing.

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Commented source and recompiled FPGA to new fpgaimg.c
This commit is contained in:
d18c7db 2009-04-16 23:09:21 +00:00
commit 1c38843b3f
3 changed files with 7687 additions and 7683 deletions
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60
fpga/testbed_lo_read.v
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@ -1,4 +1,3 @@
`include "lo_read_org.v"
`include "lo_read.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
@ -38,7 +37,7 @@ module testbed_lo_read;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
wire ssp_dout;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
@ -48,47 +47,25 @@ module testbed_lo_read;
wire cross_hi;
wire dbg;
lo_read_org #(5,10) dut1(
lo_read #(5,10) dut(
.pck0(pck0),
.ck_1356meg(ack_1356meg),
.ck_1356megb(ack_1356megb),
.pwr_lo(apwr_lo),
.pwr_hi(apwr_hi),
.pwr_oe1(apwr_oe1),
.pwr_oe2(apwr_oe2),
.pwr_oe3(apwr_oe3),
.pwr_oe4(apwr_oe4),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(assp_frame),
.ssp_din(assp_din),
.ssp_dout(assp_dout),
.ssp_clk(assp_clk),
.cross_hi(across_hi),
.cross_lo(across_lo),
.dbg(adbg),
.lo_is_125khz(lo_is_125khz)
);
lo_read #(5,10) dut2(
.pck0(pck0),
.ck_1356meg(bck_1356meg),
.ck_1356megb(bck_1356megb),
.pwr_lo(bpwr_lo),
.pwr_hi(bpwr_hi),
.pwr_oe1(bpwr_oe1),
.pwr_oe2(bpwr_oe2),
.pwr_oe3(bpwr_oe3),
.pwr_oe4(bpwr_oe4),
.adc_d(adc_d),
.adc_clk(badc_clk),
.ssp_frame(bssp_frame),
.ssp_din(bssp_din),
.ssp_dout(bssp_dout),
.ssp_clk(bssp_clk),
.cross_hi(bcross_hi),
.cross_lo(bcross_lo),
.dbg(bdbg),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.lo_is_125khz(lo_is_125khz),
.divisor(divisor)
);
@ -111,8 +88,9 @@ module testbed_lo_read;
// init inputs
pck0 = 0;
adc_d = 0;
ssp_dout = 0;
lo_is_125khz = 1;
divisor=255; //min 19, 95=125Khz, max 255
divisor = 255; //min 16, 95=125Khz, max 255
// simulate 4 A/D cycles at 125Khz
for (i = 0 ; i < 8 ; i = i + 1) begin