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Fix up small error in main osc startup delay and replace more custom defines with standard Atmel defines

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This commit is contained in:
d18c7db 2010-03-04 08:15:59 +00:00
parent 9e84fd5b73
commit 0aa4cfc2f1
5 changed files with 21 additions and 35 deletions
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2
armsrc/legicrf.c
View file

@ -34,7 +34,7 @@ static void setup_timer(void)
AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1); AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
timer = AT91C_BASE_TC1; timer = AT91C_BASE_TC1;
timer->TC_CCR = AT91C_TC_CLKDIS; timer->TC_CCR = AT91C_TC_CLKDIS;
timer->TC_CMR = TC_CMR_TCCLKS_TIMER_CLOCK3; timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK;
timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
/* At TIMER_CLOCK3 (MCK/32) */ /* At TIMER_CLOCK3 (MCK/32) */

2
armsrc/lfops.c
View file

@ -543,7 +543,7 @@ void SimulateTagLowFrequencyBidir(int divisor, int t0)
AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1); AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME; AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;
AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
AT91C_BASE_TC1->TC_CMR = TC_CMR_TCCLKS_TIMER_CLOCK1 | AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK |
AT91C_TC_ETRGEDG_RISING | AT91C_TC_ETRGEDG_RISING |
AT91C_TC_ABETRG | AT91C_TC_ABETRG |
AT91C_TC_LDRA_RISING | AT91C_TC_LDRA_RISING |

35
bootrom/bootrom.c
View file

@ -29,21 +29,22 @@ static void ConfigClocks(void)
(1<<AT91C_ID_PWMC) | (1<<AT91C_ID_PWMC) |
(1<<AT91C_ID_UDP); (1<<AT91C_ID_UDP);
// worst case scenario, with 16Mhz xtal startup delay is 14.5ms // worst case scenario, with MAINCK = 16Mhz xtal, startup delay is 1.4ms
// with a slow clock running at it worst case (max) frequency of 42khz // if SLCK slow clock runs at its worst case (max) frequency of 42khz
// max startup delay = (14.5ms*42k)/8 = 76 = 0x4C round up to 0x50 // max startup delay = (1.4ms*42k)/8 = 7.356 so round up to 8
// enable main oscillator and set startup delay // enable main oscillator and set startup delay
AT91C_BASE_PMC->PMC_MOR = AT91C_BASE_PMC->PMC_MOR =
PMC_MAIN_OSC_ENABLE | AT91C_CKGR_MOSCEN |
PMC_MAIN_OSC_STARTUP_DELAY(0x50); PMC_MAIN_OSC_STARTUP_DELAY(8);
// wait for main oscillator to stabilize // wait for main oscillator to stabilize
while ( !(AT91C_BASE_PMC->PMC_SR & PMC_MAIN_OSC_STABILIZED) ) while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS) )
; ;
// minimum PLL clock frequency is 80 MHz in range 00 (96 here so okay) // PLL output clock frequency in range 80 - 160 MHz needs CKGR_PLL = 00
// frequency is crystal * multiplier / divisor = 16Mhz * 12 / 2 = 96Mhz // PLL output clock frequency in range 150 - 180 MHz needs CKGR_PLL = 10
// PLL output is MAINCK * multiplier / divisor = 16Mhz * 12 / 2 = 96Mhz
AT91C_BASE_PMC->PMC_PLLR = AT91C_BASE_PMC->PMC_PLLR =
PMC_PLL_DIVISOR(2) | PMC_PLL_DIVISOR(2) |
PMC_PLL_COUNT_BEFORE_LOCK(0x50) | PMC_PLL_COUNT_BEFORE_LOCK(0x50) |
@ -52,23 +53,23 @@ static void ConfigClocks(void)
PMC_PLL_USB_DIVISOR(1); PMC_PLL_USB_DIVISOR(1);
// wait for PLL to lock // wait for PLL to lock
while ( !(AT91C_BASE_PMC->PMC_SR & PMC_MAIN_OSC_PLL_LOCK) ) while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) )
; ;
// we want a master clock (MCK) to be PLL clock / 2 = 96Mhz / 2 = 48Mhz // we want a master clock (MCK) to be PLL clock / 2 = 96Mhz / 2 = 48Mhz
// as per datasheet, this register must be programmed in two operations // datasheet recommends that this register is programmed in two operations
// when changing to PLL, program the prescaler first then the source // when changing to PLL, program the prescaler first then the source
AT91C_BASE_PMC->PMC_MCKR = PMC_CLK_PRESCALE_DIV_2; AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
// wait for main clock ready signal // wait for main clock ready signal
while ( !(AT91C_BASE_PMC->PMC_SR & PMC_MAIN_OSC_MCK_READY) ) while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) )
; ;
// set the source to PLL // set the source to PLL
AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | PMC_CLK_PRESCALE_DIV_2; AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 | AT91C_PMC_CSS_PLL_CLK;
// wait for main clock ready signal // wait for main clock ready signal
while ( !(AT91C_BASE_PMC->PMC_SR & PMC_MAIN_OSC_MCK_READY) ) while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) )
; ;
} }
@ -128,9 +129,9 @@ void UsbPacketReceived(uint8_t *packet, int len)
uint32_t sr; uint32_t sr;
while(!((sr = AT91C_BASE_EFC0->EFC_FSR) & MC_FLASH_STATUS_READY)) while(!((sr = AT91C_BASE_EFC0->EFC_FSR) & AT91C_MC_FRDY))
; ;
if(sr & (MC_FLASH_STATUS_LOCKE | MC_FLASH_STATUS_PROGE)) { if(sr & (AT91C_MC_LOCKE | AT91C_MC_PROGE)) {
dont_ack = 1; dont_ack = 1;
c->cmd = CMD_NACK; c->cmd = CMD_NACK;
UsbSendPacket(packet, len); UsbSendPacket(packet, len);
@ -257,7 +258,7 @@ void BootROM(void)
LED_A_OFF(); LED_A_OFF();
AT91C_BASE_EFC0->EFC_FMR = AT91C_BASE_EFC0->EFC_FMR =
MC_FLASH_MODE_FLASH_WAIT_STATES(1) | AT91C_MC_FWS_1FWS |
MC_FLASH_MODE_MASTER_CLK_IN_MHZ(48); MC_FLASH_MODE_MASTER_CLK_IN_MHZ(48);
// Initialize all system clocks // Initialize all system clocks

2
include/at91sam7s512.h
View file

@ -1415,7 +1415,7 @@ typedef struct _AT91S_TC {
#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK #define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK #define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK #define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
#define T91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK #define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK #define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 #define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0
#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 #define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1

15
include/proxmark3.h
View file

@ -20,12 +20,6 @@
#define PWM_CH_MODE_PRESCALER(x) ((x)<<0) #define PWM_CH_MODE_PRESCALER(x) ((x)<<0)
#define PWM_CHANNEL(x) (1<<(x)) #define PWM_CHANNEL(x) (1<<(x))
#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0<<0)
#define TC_CMR_TCCLKS_TIMER_CLOCK2 (1<<0)
#define TC_CMR_TCCLKS_TIMER_CLOCK3 (2<<0)
#define TC_CMR_TCCLKS_TIMER_CLOCK4 (3<<0)
#define TC_CMR_TCCLKS_TIMER_CLOCK5 (4<<0)
#define ADC_CHAN_LF 4 #define ADC_CHAN_LF 4
#define ADC_CHAN_HF 5 #define ADC_CHAN_HF 5
#define ADC_MODE_PRESCALE(x) ((x)<<8) #define ADC_MODE_PRESCALE(x) ((x)<<8)
@ -40,23 +34,14 @@
#define SSC_FRAME_MODE_BITS_IN_WORD(x) (((x)-1)<<0) #define SSC_FRAME_MODE_BITS_IN_WORD(x) (((x)-1)<<0)
#define MC_FLASH_COMMAND_KEY ((0x5a)<<24) #define MC_FLASH_COMMAND_KEY ((0x5a)<<24)
#define MC_FLASH_STATUS_READY (1<<0)
#define MC_FLASH_STATUS_LOCKE (1<<2)
#define MC_FLASH_STATUS_PROGE (1<<3)
#define MC_FLASH_MODE_FLASH_WAIT_STATES(x) ((x)<<8) #define MC_FLASH_MODE_FLASH_WAIT_STATES(x) ((x)<<8)
#define MC_FLASH_MODE_MASTER_CLK_IN_MHZ(x) (((x)+((x)/2))<<16) #define MC_FLASH_MODE_MASTER_CLK_IN_MHZ(x) (((x)+((x)/2))<<16)
#define MC_FLASH_COMMAND_PAGEN(x) ((x)<<8) #define MC_FLASH_COMMAND_PAGEN(x) ((x)<<8)
#define RST_CONTROL_KEY (0xa5<<24) #define RST_CONTROL_KEY (0xa5<<24)
#define PMC_MAIN_OSC_ENABLE (1<<0)
#define PMC_MAIN_OSC_STABILIZED (1<<0)
#define PMC_MAIN_OSC_PLL_LOCK (1<<2)
#define PMC_MAIN_OSC_MCK_READY (1<<3)
#define PMC_MAIN_OSC_STARTUP_DELAY(x) ((x)<<8) #define PMC_MAIN_OSC_STARTUP_DELAY(x) ((x)<<8)
#define PMC_PLL_DIVISOR(x) (x) #define PMC_PLL_DIVISOR(x) (x)
#define PMC_CLK_PRESCALE_DIV_2 (1<<2)
#define PMC_PLL_MULTIPLIER(x) (((x)-1)<<16) #define PMC_PLL_MULTIPLIER(x) (((x)-1)<<16)
#define PMC_PLL_COUNT_BEFORE_LOCK(x) ((x)<<8) #define PMC_PLL_COUNT_BEFORE_LOCK(x) ((x)<<8)
#define PMC_PLL_FREQUENCY_RANGE(x) ((x)<<14) #define PMC_PLL_FREQUENCY_RANGE(x) ((x)<<14)