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Hitag fixes (#887)
* don't display error message during 'lf search' when no Hitag tag is present * remove superfluous options in 'lf hitag read' * fix setting of default threshold when selecting FPGA_CMD_SET_EDGE_DETECT_THRESHOLD major mode * some refactoring
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pwpiwi
GitHub
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7 changed files with 66 additions and 56 deletions
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@ -3,6 +3,26 @@
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// iZsh <izsh at fail0verflow.com>, June 2014
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//-----------------------------------------------------------------------------
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// Defining commands, modes and options. This must be aligned to the definitions in fpgaloader.h
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// Note: the definitions here are without shifts
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// Commands:
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`define FPGA_CMD_SET_CONFREG 1
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`define FPGA_CMD_SET_DIVISOR 2
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`define FPGA_CMD_SET_EDGE_DETECT_THRESHOLD 3
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// Major modes:
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`define FPGA_MAJOR_MODE_LF_ADC 0
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`define FPGA_MAJOR_MODE_LF_EDGE_DETECT 1
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`define FPGA_MAJOR_MODE_LF_PASSTHRU 2
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// Options for LF_ADC
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`define FPGA_LF_ADC_READER_FIELD 1
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// Options for LF_EDGE_DETECT
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`define FPGA_LF_EDGE_DETECT_READER_FIELD 1
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`define FPGA_LF_EDGE_DETECT_TOGGLE_MODE 2
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`include "lo_read.v"
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`include "lo_passthru.v"
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`include "lo_edge_detect.v"
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@ -30,21 +50,23 @@ module fpga_lf(
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reg [15:0] shift_reg;
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reg [7:0] divisor;
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reg [8:0] conf_word;
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reg [7:0] user_byte1;
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reg [7:0] lf_ed_threshold;
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always @(posedge ncs)
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begin
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case (shift_reg[15:12])
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4'b0001: // FPGA_CMD_SET_CONFREG
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`FPGA_CMD_SET_CONFREG:
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begin
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conf_word <= shift_reg[8:0];
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if (shift_reg[8:0] == 9'b000000001)
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begin // LF edge detect
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user_byte1 <= 127; // default threshold
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if (shift_reg[8:6] == `FPGA_MAJOR_MODE_LF_EDGE_DETECT)
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begin
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lf_ed_threshold <= 127; // default threshold
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end
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end
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4'b0010: divisor <= shift_reg[7:0]; // FPGA_CMD_SET_DIVISOR
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4'b0011: user_byte1 <= shift_reg[7:0]; // FPGA_CMD_SET_USER_BYTE1
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`FPGA_CMD_SET_DIVISOR:
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divisor <= shift_reg[7:0];
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`FPGA_CMD_SET_EDGE_DETECT_THRESHOLD:
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lf_ed_threshold <= shift_reg[7:0];
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endcase
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end
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@ -62,7 +84,6 @@ wire [2:0] major_mode = conf_word[8:6];
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// For the low-frequency configuration:
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wire lf_field = conf_word[0];
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wire lf_ed_toggle_mode = conf_word[1]; // for lo_edge_detect
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wire [7:0] lf_ed_threshold = user_byte1;
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//-----------------------------------------------------------------------------
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// And then we instantiate the modules corresponding to each of the FPGA's
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@ -106,17 +127,17 @@ lo_edge_detect le(
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// 001 -- LF edge detect (generic)
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// 010 -- LF passthrough
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mux8 mux_ssp_clk (major_mode, ssp_clk, lr_ssp_clk, le_ssp_clk, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_ssp_din (major_mode, ssp_din, lr_ssp_din, 1'b0, lp_ssp_din, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, le_ssp_frame, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe1 (major_mode, pwr_oe1, lr_pwr_oe1, le_pwr_oe1, lp_pwr_oe1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe2 (major_mode, pwr_oe2, lr_pwr_oe2, le_pwr_oe2, lp_pwr_oe2, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe3 (major_mode, pwr_oe3, lr_pwr_oe3, le_pwr_oe3, lp_pwr_oe3, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe4 (major_mode, pwr_oe4, lr_pwr_oe4, le_pwr_oe4, lp_pwr_oe4, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, le_pwr_lo, lp_pwr_lo, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, le_pwr_hi, lp_pwr_hi, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, le_adc_clk, lp_adc_clk, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_dbg (major_mode, dbg, lr_dbg, le_dbg, lp_dbg, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_ssp_clk (major_mode, ssp_clk, lr_ssp_clk, le_ssp_clk, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_ssp_din (major_mode, ssp_din, lr_ssp_din, 1'b0, lp_ssp_din, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, le_ssp_frame, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe1 (major_mode, pwr_oe1, lr_pwr_oe1, le_pwr_oe1, lp_pwr_oe1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe2 (major_mode, pwr_oe2, lr_pwr_oe2, le_pwr_oe2, lp_pwr_oe2, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe3 (major_mode, pwr_oe3, lr_pwr_oe3, le_pwr_oe3, lp_pwr_oe3, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe4 (major_mode, pwr_oe4, lr_pwr_oe4, le_pwr_oe4, lp_pwr_oe4, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, le_pwr_lo, lp_pwr_lo, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, le_pwr_hi, lp_pwr_hi, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, le_adc_clk, lp_adc_clk, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_dbg (major_mode, dbg, lr_dbg, le_dbg, lp_dbg, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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// In all modes, let the ADC's outputs be enabled.
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assign adc_noe = 1'b0;
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