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CHG: FPC connector tests. Device -> Client communications works.
Adjust armsrc/Makefile and client/Makefile to include the -DWITH_FPC flag to compile with FPC enabled.
This commit is contained in:
Chris
parent
aa3b322d0f
commit
f8c33af1da
7 changed files with 123 additions and 119 deletions
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@ -56,8 +56,8 @@ uint8_t cmd_send(uint64_t cmd, uint64_t arg0, uint64_t arg1, uint64_t arg2, void
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sendlen = usb_write( (uint8_t*)&txcmd, sizeof(UsbCommand) );
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#ifdef WITH_FPC
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usart_init();
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usart_writebuffer( (uint8_t*)&txcmd, sizeof(UsbCommand) );
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// usart_init();
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// usart_writebuffer( (uint8_t*)&txcmd, sizeof(UsbCommand) );
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#endif
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return sendlen;
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114
common/usart.c
114
common/usart.c
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@ -1,6 +1,6 @@
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//-----------------------------------------------------------------------------
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// Iceman, July 2018
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// edists by - Anticat, August 2018
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// edits by - Anticat, August 2018
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//
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// This code is licensed to you under the terms of the GNU GPL, version 2 or,
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// at your option, any later version. See the LICENSE.txt file for the text of
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@ -14,7 +14,7 @@
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#define AT91_BAUD_RATE 115200
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volatile AT91PS_USART pUS1 = AT91C_BASE_US1;
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volatile AT91PS_PIO pPIOA = AT91C_BASE_PIOA;
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volatile AT91PS_PIO pPIO = AT91C_BASE_PIOA;
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volatile AT91PS_PDC pPDC = AT91C_BASE_PDC_US1;
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/*
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@ -39,90 +39,53 @@ void usart_close(void) {
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}
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*/
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static uint8_t outbuf[sizeof(UsbCommand)];
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//static uint8_t inbuf[sizeof(UsbCommand)];
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static uint8_t us_outbuf[sizeof(UsbCommand)];
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/// Reads data from an USART peripheral
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/// \param data Pointer to the buffer where the received data will be stored.
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/// \param len Size of the data buffer (in bytes).
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inline int usart_readbuffer(uint8_t *data, size_t len) {
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inline int16_t usart_readbuffer(uint8_t *data, size_t len) {
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pUS1->US_PTSR = AT91C_PDC_TXTEN;
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pUS1->US_PTCR = AT91C_PDC_TXTEN;
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// Check if the first PDC bank is free
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if (!(pUS1->US_RCR)) {
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pUS1->US_RPR = (uint32_t)data;
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pUS1->US_RCR = len;
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pUS1->US_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTDIS;
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return 2;
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}
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// Check if the second PDC bank is free
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else if (!(pUS1->US_RNCR)) {
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pUS1->US_RNPR = (uint32_t)data;
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pUS1->US_RNCR = len;
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pUS1->US_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTDIS;
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return 1;
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} else {
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return 0;
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}
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/*
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pPDC->PDC_PTSR = AT91C_PDC_RXTEN;
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pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
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//check if data is available
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if (pPDC->PDC_RCR != 0) return -1;
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memcpy(data, inbuf, len);
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//start next transfer
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pPDC->PDC_RNPR = (uint32_t)inbuf;
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pPDC->PDC_RNCR = sizeof(inbuf);
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return sizeof(inbuf);
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*/
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}
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/*
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int16_t usart_writebuffer(uint8_t *data, size_t len) {
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// pUS1->US_PTSR = AT91C_PDC_TXTEN;
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pUS1->US_PTCR = AT91C_PDC_TXTEN;
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// if buffer is sent
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if (pUS1->US_TCR != 0) return -1;
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memcpy(outbuf, data, len);
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//start next transfer
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pUS1->US_TNPR = (uint32_t)outbuf;
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pUS1->US_TNCR = sizeof(outbuf);
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return sizeof(outbuf);
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}
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*/
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// works.
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// transfer to client
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// transfer from device to client
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inline int16_t usart_writebuffer(uint8_t *data, size_t len) {
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pUS1->US_PTSR = AT91C_PDC_TXTEN;
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pUS1->US_PTCR = AT91C_PDC_TXTEN;
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// Check if the first PDC bank is free
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if (!(pUS1->US_TCR)) {
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memcpy(outbuf, data, len);
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pUS1->US_TPR = (uint32_t)outbuf;
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pUS1->US_TCR = sizeof(outbuf);
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memcpy(us_outbuf, data, len);
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pUS1->US_TPR = (uint32_t)us_outbuf;
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pUS1->US_TCR = sizeof(us_outbuf);
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pUS1->US_PTCR = AT91C_PDC_TXTEN | AT91C_PDC_RXTDIS;
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return 2;
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}
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// Check if the second PDC bank is free
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else if (!(pUS1->US_TNCR)) {
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memcpy(outbuf, data, len);
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pUS1->US_TNPR = (uint32_t)outbuf;
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pUS1->US_TNCR = sizeof(outbuf);
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memcpy(us_outbuf, data, len);
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pUS1->US_TNPR = (uint32_t)us_outbuf;
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pUS1->US_TNCR = sizeof(us_outbuf);
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pUS1->US_PTCR = AT91C_PDC_TXTEN | AT91C_PDC_RXTDIS;
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return 1;
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} else {
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return 0;
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@ -132,19 +95,20 @@ inline int16_t usart_writebuffer(uint8_t *data, size_t len) {
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void usart_init(void) {
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// disable & reset receiver / transmitter for configuration
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pUS1->US_CR = (AT91C_US_RSTRX | AT91C_US_RSTTX);
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pUS1->US_CR = (AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS);
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//enable the USART1 Peripheral clock
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AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_US1);
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// disable PIO control of receive / transmit pins
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pPIOA->PIO_PDR |= (AT91C_PA21_RXD1 | AT91C_PA22_TXD1);
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pPIO->PIO_PDR |= (AT91C_PA21_RXD1 | AT91C_PA22_TXD1);
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// enable peripheral mode A on receive / transmit pins
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pPIOA->PIO_ASR |= (AT91C_PA21_RXD1 | AT91C_PA22_TXD1);
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pPIO->PIO_ASR |= (AT91C_PA21_RXD1 | AT91C_PA22_TXD1);
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pPIO->PIO_BSR = 0;
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// enable pull-up on receive / transmit pins (see 31.5.1 I/O Lines)
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pPIOA->PIO_PPUER |= (AT91C_PA21_RXD1 | AT91C_PA22_TXD1);
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pPIO->PIO_PPUER |= (AT91C_PA21_RXD1 | AT91C_PA22_TXD1);
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// set mode
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pUS1->US_MR = AT91C_US_USMODE_NORMAL | // normal mode
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@ -154,8 +118,19 @@ void usart_init(void) {
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AT91C_US_NBSTOP_1_BIT | // 1 stop bit
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AT91C_US_CHMODE_NORMAL; // channel mode: normal
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// all interrupts disabled
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pUS1->US_IDR = 0xFFFF;
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// iceman, setting 115200 doesn't work. Only speed I got to work is 9600.
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// something fishy with the AT91SAM7S512 USART.. Or I missed something
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// For a nice detailed sample, interrupt driven but still relevant.
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// See https://www.sparkfun.com/datasheets/DevTools/SAM7/at91sam7%20serial%20communications.pdf
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// set baudrate to 115200
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pUS1->US_BRGR = (48UL*1000*1000) / (115200*16);
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// 115200 * 16 == 1843200
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//
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//pUS1->US_BRGR = (48UL*1000*1000) / (9600*16);
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pUS1->US_BRGR = 48054841 / (9600 << 4);
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// Write the Timeguard Register
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pUS1->US_TTGR = 0;
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@ -163,23 +138,6 @@ void usart_init(void) {
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pUS1->US_FIDI = 0;
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pUS1->US_IF = 0;
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/*
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//Empty PDC
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pUS1->US_RNPR = (uint32_t)(char *)0;
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pUS1->US_RNCR = 0;
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pUS1->US_RPR = (uint32_t)(char *)0;
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pUS1->US_RCR = 0;
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pUS1->US_TNPR = (uint32_t)(char *)0;
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pUS1->US_TNCR = 0;
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pUS1->US_TPR = (uint32_t)(char *)0;
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pUS1->US_TCR = 0;
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*/
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//pUS1->US_PTCR = (AT91C_PDC_RXTEN | AT91C_PDC_TXTEN);
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//pUS1->US_PTSR = (AT91C_PDC_RXTEN | AT91C_PDC_TXTEN);
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// re-enable receiver / transmitter
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pUS1->US_CR = (AT91C_US_RXEN | AT91C_US_TXEN);
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}
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@ -7,6 +7,6 @@
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void usart_init(void);
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void usart_close(void);
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int usart_readbuffer(uint8_t *data, size_t len);
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int16_t usart_readbuffer(uint8_t *data, size_t len);
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int16_t usart_writebuffer(uint8_t *data, size_t len);
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#endif
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