chg: reverting old @satsuoni felica changes.

chg: applied @pwpiwi 's fixes for iso 14B / 15

fpga/hi_read_tx.v

@@ -12,7 +12,7 @@ module hi_read_tx(
     ssp_frame, ssp_din, ssp_dout, ssp_clk,
     cross_hi, cross_lo,
     dbg,
-    shallow_modulation, speed, power
+    shallow_modulation
 );
     input pck0, ck_1356meg, ck_1356megb;
     output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
@@ -23,46 +23,36 @@ module hi_read_tx(
     input cross_hi, cross_lo;
     output dbg;
     input shallow_modulation;
-    input [1:0] speed;
-    input power;
 
+// low frequency outputs, not relevant
+assign pwr_lo = 1'b0;
+assign pwr_oe2 = 1'b0;
+	
 // The high-frequency stuff. For now, for testing, just bring out the carrier,
 // and allow the ARM to modulate it over the SSP.
 reg pwr_hi;
 reg pwr_oe1;
-reg pwr_oe2;
 reg pwr_oe3;
 reg pwr_oe4;
+
 always @(ck_1356megb or ssp_dout or shallow_modulation)
-begin
-if (power)
 begin
     if(shallow_modulation)
     begin
         pwr_hi <= ck_1356megb;
-        pwr_oe1 <= ~ssp_dout;
-        pwr_oe2 <= ~ssp_dout;
-        pwr_oe3 <= ~ssp_dout;
-        pwr_oe4 <= 1'b0;
+        pwr_oe1 <= 1'b0;
+        pwr_oe3 <= 1'b0;
+        pwr_oe4 <= ~ssp_dout;
     end
     else
     begin
         pwr_hi <= ck_1356megb & ssp_dout;
         pwr_oe1 <= 1'b0;
-        pwr_oe2 <= 1'b0;
         pwr_oe3 <= 1'b0;
         pwr_oe4 <= 1'b0;
     end
 end
-else
-begin
-       pwr_hi <= 1'b0;
-        pwr_oe1 <= 1'b0;
-        pwr_oe2 <= 1'b0;
-        pwr_oe3 <= 1'b0;
-        pwr_oe4 <= ~ssp_dout;
-end    
-end
+
 
 // Then just divide the 13.56 MHz clock down to produce appropriate clocks
 // for the synchronous serial port.
@@ -72,7 +62,7 @@ reg [6:0] hi_div_by_128;
 always @(posedge ck_1356meg)
     hi_div_by_128 <= hi_div_by_128 + 1;
 
-assign ssp_clk = speed[1]? (speed[0]? hi_div_by_128[3]: hi_div_by_128[4]) : (speed[0]? hi_div_by_128[5]: hi_div_by_128[6]);
+assign ssp_clk = hi_div_by_128[6];
 
 reg [2:0] hi_byte_div;
 
@@ -89,14 +79,13 @@ assign adc_clk = ck_1356meg;
 reg after_hysteresis;
 always @(negedge adc_clk)
 begin
-    if(& adc_d[7:4]) after_hysteresis <= 1'b1;
+    if(& adc_d[7:0]) after_hysteresis <= 1'b1;
     else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;
 end
 
 
 assign ssp_din = after_hysteresis;
 
-assign pwr_lo = 1'b0;
 assign dbg = ssp_din;
 
 endmodule