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11 changed files with 177 additions and 177 deletions
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@ -141,16 +141,16 @@ void FpgaSetupSsc(void) {
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// Now set up the SSC proper, starting from a known state.
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AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
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// RX clock comes from TX clock, RX starts on Transmit Start,
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// data and frame signal is sampled on falling edge of RK
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// RX clock comes from TX clock, RX starts on Transmit Start,
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// data and frame signal is sampled on falling edge of RK
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AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);
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// 8 bits per transfer, no loopback, MSB first, 1 transfer per sync
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// pulse, no output sync
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AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) | AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
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// TX clock comes from TK pin, no clock output, outputs change on falling
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// edge of TK, frame sync is sampled on rising edge of TK, start TX on rising edge of TF
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// TX clock comes from TK pin, no clock output, outputs change on falling
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// edge of TK, frame sync is sampled on rising edge of TK, start TX on rising edge of TF
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AT91C_BASE_SSC->SSC_TCMR = SSC_CLOCK_MODE_SELECT(2) | SSC_CLOCK_MODE_START(5);
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// tx framing is the same as the rx framing
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@ -439,7 +439,7 @@ void FpgaDownloadAndGo(int bitstream_version) {
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// Send a 16 bit command/data pair to the FPGA.
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// The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
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// where C is the 4 bit command and D is the 12 bit data
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//
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//
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// @params cmd and v gets or over eachother. Take careful note of overlapping bits.
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//-----------------------------------------------------------------------------
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void FpgaSendCommand(uint16_t cmd, uint16_t v) {
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@ -461,11 +461,11 @@ void FpgaWriteConfWord(uint16_t v) {
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// enable/disable FPGA internal tracing
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//-----------------------------------------------------------------------------
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void FpgaEnableTracing(void) {
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FpgaSendCommand(FPGA_CMD_TRACE_ENABLE, 1);
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FpgaSendCommand(FPGA_CMD_TRACE_ENABLE, 1);
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}
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void FpgaDisableTracing(void) {
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FpgaSendCommand(FPGA_CMD_TRACE_ENABLE, 0);
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FpgaSendCommand(FPGA_CMD_TRACE_ENABLE, 0);
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}
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//-----------------------------------------------------------------------------
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