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Add fpga-xc3s100e and icopyx support

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This commit is contained in:
Philippe Teuwen 2021-08-21 23:43:06 +02:00
commit e79fb92074
106 changed files with 4213 additions and 85 deletions
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16
armsrc/appmain.c
View file

@ -212,11 +212,7 @@ static void MeasureAntennaTuning(void) {
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER);
SpinDelay(50);
#if defined RDV4
payload.v_hf = (MAX_ADC_HF_VOLTAGE_RDV40 * SumAdc(ADC_CHAN_HF_RDV40, 32)) >> 15;
#else
payload.v_hf = (MAX_ADC_HF_VOLTAGE * SumAdc(ADC_CHAN_HF, 32)) >> 15;
#endif
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
reply_ng(CMD_MEASURE_ANTENNA_TUNING, PM3_SUCCESS, (uint8_t *)&payload, sizeof(payload));
@ -226,11 +222,7 @@ static void MeasureAntennaTuning(void) {
// Measure HF in milliVolt
static uint16_t MeasureAntennaTuningHfData(void) {
#if defined RDV4
return (MAX_ADC_HF_VOLTAGE_RDV40 * SumAdc(ADC_CHAN_HF_RDV40, 32)) >> 15;
#else
return (MAX_ADC_HF_VOLTAGE * SumAdc(ADC_CHAN_HF, 32)) >> 15;
#endif
}
@ -610,12 +602,8 @@ void ListenReaderField(uint8_t limit) {
if (limit == HF_ONLY) {
#if defined RDV4
// iceman, useless, since we are measuring readerfield, not our field. My tests shows a max of 20v from a reader.
hf_av = hf_max = (MAX_ADC_HF_VOLTAGE_RDV40 * SumAdc(ADC_CHAN_HF_RDV40, 32)) >> 15;
#else
hf_av = hf_max = (MAX_ADC_HF_VOLTAGE * SumAdc(ADC_CHAN_HF, 32)) >> 15;
#endif
Dbprintf("HF 13.56MHz Baseline: %dmV", hf_av);
hf_baseline = hf_av;
}
@ -666,11 +654,7 @@ void ListenReaderField(uint8_t limit) {
LED_B_OFF();
}
#if defined RDV4
hf_av_new = (MAX_ADC_HF_VOLTAGE_RDV40 * SumAdc(ADC_CHAN_HF_RDV40, 32)) >> 15;
#else
hf_av_new = (MAX_ADC_HF_VOLTAGE * SumAdc(ADC_CHAN_HF, 32)) >> 15;
#endif
// see if there's a significant change
if (ABS(hf_av - hf_av_new) > REPORT_CHANGE) {
Dbprintf("HF 13.56MHz Field Change: %5dmV", hf_av_new);

11
armsrc/appmain.h
View file

@ -18,11 +18,14 @@ extern bool g_hf_field_active;
void hf_field_off(void);
int tearoff_hook(void);
// ADC Vref = 3300mV, and an (10M+1M):1M voltage divider on the HF input can measure voltages up to 36300 mV
#define MAX_ADC_HF_VOLTAGE 36300
#if defined RDV4 || defined ICOPYX
// ADC Vref = 3300mV, and an (10000k+240k):240k voltage divider on the LF input can measure voltages up to 140800 mV
#define MAX_ADC_HF_VOLTAGE 140800
#else
// ADC Vref = 3300mV, and an (10M+1M):1M voltage divider on the HF input can measure voltages up to 36300 mV
#define MAX_ADC_HF_VOLTAGE 36300
#endif
// ADC Vref = 3300mV, (240k-10M):240k voltage divider, 140800 mV
#define MAX_ADC_HF_VOLTAGE_RDV40 140800
// ADC Vref = 3300mV, and an (10000k+240k):240k voltage divider on the LF input can measure voltages up to 140800 mV
#define MAX_ADC_LF_VOLTAGE 140800
extern int ToSendMax;

5
armsrc/felica.c
View file

@ -445,8 +445,11 @@ static void iso18092_setup(uint8_t fpga_minor_mode) {
if (g_dbglevel >= DBG_DEBUG) Dbprintf("Start iso18092_setup");
LEDsoff();
#if defined XC3
FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
#else
FpgaDownloadAndGo(FPGA_BITSTREAM_HF_FELICA);
#endif
// allocate command receive buffer
BigBuf_free();
BigBuf_Clear_ext(false);

78
armsrc/fpgaloader.c
View file

@ -269,10 +269,11 @@ static void DownloadFPGA_byte(uint8_t w) {
// Download the fpga image starting at current stream position with length FpgaImageLen bytes
static void DownloadFPGA(int bitstream_version, int FpgaImageLen, lz4_streamp_t compressed_fpga_stream, uint8_t *output_buffer) {
int i = 0;
#if !defined XC3
AT91C_BASE_PIOA->PIO_OER = GPIO_FPGA_ON;
AT91C_BASE_PIOA->PIO_PER = GPIO_FPGA_ON;
HIGH(GPIO_FPGA_ON); // ensure everything is powered on
#endif
SpinDelay(50);
@ -285,7 +286,13 @@ static void DownloadFPGA(int bitstream_version, int FpgaImageLen, lz4_streamp_t
// PIO controls the following pins
AT91C_BASE_PIOA->PIO_PER =
GPIO_FPGA_NINIT |
#if defined XC3
//3S100E M2 & M3 PIO ENA
GPIO_SPCK |
GPIO_MOSI |
#endif
GPIO_FPGA_DONE;
// Enable pull-ups
AT91C_BASE_PIOA->PIO_PPUER =
GPIO_FPGA_NINIT |
@ -299,8 +306,19 @@ static void DownloadFPGA(int bitstream_version, int FpgaImageLen, lz4_streamp_t
AT91C_BASE_PIOA->PIO_OER =
GPIO_FPGA_NPROGRAM |
GPIO_FPGA_CCLK |
#if defined XC3
//3S100E M2 & M3 OUTPUT ENA
GPIO_SPCK |
GPIO_MOSI |
#endif
GPIO_FPGA_DIN;
#if defined XC3
//3S100E M2 & M3 OUTPUT HIGH
HIGH(GPIO_SPCK);
HIGH(GPIO_MOSI);
#endif
// enter FPGA configuration mode
LOW(GPIO_FPGA_NPROGRAM);
SpinDelay(50);
@ -319,6 +337,13 @@ static void DownloadFPGA(int bitstream_version, int FpgaImageLen, lz4_streamp_t
return;
}
#if defined XC3
//3S100E M2 & M3 RETURN TO NORMAL
LOW(GPIO_SPCK);
LOW(GPIO_MOSI);
AT91C_BASE_PIOA->PIO_PDR = GPIO_SPCK | GPIO_MOSI;
#endif
for (i = 0; i < FpgaImageLen; i++) {
int b = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
if (b < 0) {
@ -396,6 +421,43 @@ static int bitparse_find_section(int bitstream_version, char section_name, uint3
return result;
}
//----------------------------------------------------------------------------
// Change FPGA image status, if image loaded.
// bitstream_version is your new fpga image version
// return true if can change.
// return false if image is unloaded.
//----------------------------------------------------------------------------
#if defined XC3
static bool FpgaConfCurrentMode(int bitstream_version) {
// fpga "XC3S100E" image merge
// If fpga image is no init
// We need load hf_lf_allinone.bit
if (downloaded_bitstream != 0) {
// test start
// PIO controls the following pins
AT91C_BASE_PIOA->PIO_PER = GPIO_FPGA_SWITCH;
// These pins are outputs
AT91C_BASE_PIOA->PIO_OER = GPIO_FPGA_SWITCH;
// try to turn off antenna
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
if (bitstream_version == FPGA_BITSTREAM_LF) {
LOW(GPIO_FPGA_SWITCH);
}
else {
HIGH(GPIO_FPGA_SWITCH);
}
// update downloaded_bitstream
downloaded_bitstream = bitstream_version;
// turn off antenna
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
return true;
}
return false;
}
#endif
//----------------------------------------------------------------------------
// Check which FPGA image is currently loaded (if any). If necessary
// decompress and load the correct (HF or LF) image to the FPGA
@ -408,6 +470,14 @@ void FpgaDownloadAndGo(int bitstream_version) {
return;
}
#if defined XC3
// If we can change image version
// direct return.
if (FpgaConfCurrentMode(bitstream_version)) {
return;
}
#endif
// Send waiting time extension request as this will take a while
send_wtx(1500);
@ -431,6 +501,12 @@ void FpgaDownloadAndGo(int bitstream_version) {
downloaded_bitstream = bitstream_version;
}
#if defined XC3
// first download fpga image to hf
// we need to change fpga status to hf
FpgaConfCurrentMode(bitstream_version);
#endif
// turn off antenna
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);

34
armsrc/iso14443a.c
View file

@ -1972,11 +1972,7 @@ int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *par) {
ADC_MODE_STARTUP_TIME(1) |
ADC_MODE_SAMPLE_HOLD_TIME(15);
#if defined RDV4
AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF_RDV40);
#else
AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF);
#endif
// start ADC
AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
@ -2003,35 +1999,6 @@ int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *par) {
++check;
// test if the field exists
#if defined RDV4
if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF_RDV40)) {
analogCnt++;
analogAVG += (AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF_RDV40] & 0x3FF);
AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
if (analogCnt >= 32) {
if ((MAX_ADC_HF_VOLTAGE_RDV40 * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) {
if (timer == 0) {
timer = GetTickCount();
} else {
// 50ms no field --> card to idle state
if (GetTickCountDelta(timer) > 50) {
return 2;
}
}
} else {
timer = 0;
}
analogCnt = 0;
analogAVG = 0;
}
}
#else
if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) {
analogCnt++;
@ -2059,7 +2026,6 @@ int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *par) {
analogAVG = 0;
}
}
#endif
// receive and test the miller decoding
if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {

8
armsrc/iso14443b.c
View file

@ -772,11 +772,7 @@ void SimulateIso14443bTag(uint8_t *pupi) {
// find reader field
if (cardSTATE == SIM_NOFIELD) {
#if defined RDV4
vHf = (MAX_ADC_HF_VOLTAGE_RDV40 * SumAdc(ADC_CHAN_HF_RDV40, 32)) >> 15;
#else
vHf = (MAX_ADC_HF_VOLTAGE * SumAdc(ADC_CHAN_HF, 32)) >> 15;
#endif
if (vHf > MF_MINFIELDV) {
cardSTATE = SIM_IDLE;
LED_A_ON();
@ -976,11 +972,7 @@ void Simulate_iso14443b_srx_tag(uint8_t *uid) {
// find reader field
if (cardSTATE == SIM_NOFIELD) {
#if defined RDV4
vHf = (MAX_ADC_HF_VOLTAGE_RDV40 * SumAdc(ADC_CHAN_HF_RDV40, 32)) >> 15;
#else
vHf = (MAX_ADC_HF_VOLTAGE * SumAdc(ADC_CHAN_HF, 32)) >> 15;
#endif
if (vHf > MF_MINFIELDV) {
cardSTATE = SIM_IDLE;
LED_A_ON();

4
armsrc/iso15693.c
View file

@ -1727,11 +1727,7 @@ void SimTagIso15693(uint8_t *uid) {
// find reader field
if (chip_state == NO_FIELD) {
#if defined RDV4
vHf = (MAX_ADC_HF_VOLTAGE_RDV40 * SumAdc(ADC_CHAN_HF_RDV40, 32)) >> 15;
#else
vHf = (MAX_ADC_HF_VOLTAGE * SumAdc(ADC_CHAN_HF, 32)) >> 15;
#endif
if (vHf > MF_MINFIELDV) {
chip_state = IDLE;
LED_A_ON();

4
armsrc/mifaresim.c
View file

@ -543,11 +543,7 @@ void Mifare1ksim(uint16_t flags, uint8_t exitAfterNReads, uint8_t *datain, uint1
// find reader field
if (cardSTATE == MFEMUL_NOFIELD) {
#if defined RDV4
vHf = (MAX_ADC_HF_VOLTAGE_RDV40 * SumAdc(ADC_CHAN_HF_RDV40, 32)) >> 15;
#else
vHf = (MAX_ADC_HF_VOLTAGE * SumAdc(ADC_CHAN_HF, 32)) >> 15;
#endif
if (vHf > MF_MINFIELDV) {
cardSTATE_TO_IDLE();

4
armsrc/thinfilm.c
View file

@ -51,11 +51,7 @@ void ReadThinFilm(void) {
static uint16_t FpgaSendQueueDelay;
static uint16_t ReadReaderField(void) {
#if defined RDV4
return AvgAdc(ADC_CHAN_HF_RDV40);
#else
return AvgAdc(ADC_CHAN_HF);
#endif
}
static void CodeThinfilmAsTag(const uint8_t *cmd, uint16_t len) {