mirror of
https://github.com/RfidResearchGroup/proxmark3.git
synced 2025-08-21 05:43:48 -07:00
- improved reader sensitivity for 14443a cards (FPGA change!)
- implemented ISO 14443A anticollision loop See http://www.proxmark.org/forum/viewtopic.php?id=1797 further details
This commit is contained in:
micki.held@gmx.de
parent
6cacefa48d
commit
e691fc45bc
9 changed files with 428 additions and 388 deletions
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@ -12,11 +12,11 @@ fpga.ngc: fpga.v fpga.ucf xst.scr util.v lo_edge_detect.v lo_read.v lo_passthru.
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fpga.ngd: fpga.ngc
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$(DELETE) fpga.ngd
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$(XILINX_TOOLS_PREFIX)ngdbuild -aul -p xc2s30-6vq100 -nt timestamp -uc fpga.ucf fpga.ngc fpga.ngd
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$(XILINX_TOOLS_PREFIX)ngdbuild -aul -p xc2s30-5-vq100 -nt timestamp -uc fpga.ucf fpga.ngc fpga.ngd
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fpga.ncd: fpga.ngd
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$(DELETE) fpga.ncd
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$(XILINX_TOOLS_PREFIX)map -p xc2s30-6vq100 fpga.ngd
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$(XILINX_TOOLS_PREFIX)map -p xc2s30-5-vq100 fpga.ngd
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fpga-placed.ncd: fpga.ncd
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$(DELETE) fpga-placed.ncd
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BIN
fpga/fpga.bit
BIN
fpga/fpga.bit
Binary file not shown.
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@ -39,3 +39,16 @@ NET "ssp_frame" LOC = "P31" ;
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#PACE: Start of PACE Prohibit Constraints
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#PACE: End of Constraints generated by PACE
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# definition of Clock nets:
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NET "ck_1356meg" TNM_NET = "clk_net_1356" ;
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NET "ck_1356megb" TNM_NET = "clk_net_1356b" ;
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NET "pck0" TNM_NET = "clk_net_pck0" ;
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NET "spck" TNM_NET = "clk_net_spck" ;
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# Timing specs of clock nets:
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TIMEGRP "clk_net_1356_all" = "clk_net_1356" "clk_net_1356b" ;
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TIMESPEC "TS_1356MHz" = PERIOD "clk_net_1356_all" 74 ns HIGH 37 ns ;
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TIMESPEC "TS_24MHz" = PERIOD "clk_net_pck0" 42 ns HIGH 21 ns ;
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TIMESPEC "TS_4MHz" = PERIOD "clk_net_spck" 250 ns HIGH 125 ns ;
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34
fpga/fpga.v
34
fpga/fpga.v
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@ -22,17 +22,17 @@
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`include "util.v"
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module fpga(
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spcki, miso, mosi, ncs,
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pck0i, ck_1356meg, ck_1356megb,
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spck, miso, mosi, ncs,
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pck0, ck_1356meg, ck_1356megb,
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pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
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adc_d, adc_clk, adc_noe,
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ssp_frame, ssp_din, ssp_dout, ssp_clk,
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cross_hi, cross_lo,
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dbg
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);
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input spcki, mosi, ncs;
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input spck, mosi, ncs;
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output miso;
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input pck0i, ck_1356meg, ck_1356megb;
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input pck0, ck_1356meg, ck_1356megb;
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output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
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input [7:0] adc_d;
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output adc_clk, adc_noe;
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@ -42,15 +42,17 @@ module fpga(
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output dbg;
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//assign pck0 = pck0i;
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IBUFG #(.IOSTANDARD("DEFAULT") ) pck0b(
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.O(pck0),
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.I(pck0i)
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);
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// IBUFG #(.IOSTANDARD("DEFAULT") ) pck0b(
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// .O(pck0),
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// .I(pck0i)
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// );
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//assign spck = spcki;
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IBUFG #(.IOSTANDARD("DEFAULT") ) spckb(
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.O(spck),
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.I(spcki)
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);
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// IBUFG #(.IOSTANDARD("DEFAULT") ) spckb(
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// .O(spck),
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// .I(spcki)
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// );
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//-----------------------------------------------------------------------------
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// The SPI receiver. This sets up the configuration word, which the rest of
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// the logic looks at to determine how to connect the A/D and the coil
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@ -68,8 +70,8 @@ reg [7:0] conf_word;
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always @(posedge ncs)
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begin
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case(shift_reg[15:12])
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4'b0001: conf_word <= shift_reg[7:0];
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4'b0010: divisor <= shift_reg[7:0];
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4'b0001: conf_word <= shift_reg[7:0]; // FPGA_CMD_SET_CONFREG
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4'b0010: divisor <= shift_reg[7:0]; // FPGA_CMD_SET_DIVISOR
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endcase
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end
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@ -202,7 +204,7 @@ hi_iso14443a hisn(
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mux8 mux_ssp_clk (major_mode, ssp_clk, lr_ssp_clk, ls_ssp_clk, ht_ssp_clk, hrxc_ssp_clk, hs_ssp_clk, hisn_ssp_clk, lp_ssp_clk, 1'b0);
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mux8 mux_ssp_din (major_mode, ssp_din, lr_ssp_din, ls_ssp_din, ht_ssp_din, hrxc_ssp_din, hs_ssp_din, hisn_ssp_din, lp_ssp_din, 1'b0);
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mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, ls_ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, lp_ssp_frame, 1'b0);
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mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, ls_ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, lp_ssp_frame, 1'b0);
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mux8 mux_pwr_oe1 (major_mode, pwr_oe1, lr_pwr_oe1, ls_pwr_oe1, ht_pwr_oe1, hrxc_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, lp_pwr_oe1, 1'b0);
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mux8 mux_pwr_oe2 (major_mode, pwr_oe2, lr_pwr_oe2, ls_pwr_oe2, ht_pwr_oe2, hrxc_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, lp_pwr_oe2, 1'b0);
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mux8 mux_pwr_oe3 (major_mode, pwr_oe3, lr_pwr_oe3, ls_pwr_oe3, ht_pwr_oe3, hrxc_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, lp_pwr_oe3, 1'b0);
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@ -210,7 +212,7 @@ mux8 mux_pwr_oe4 (major_mode, pwr_oe4, lr_pwr_oe4, ls_pwr_oe4, ht_pwr_oe4
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mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, ls_pwr_lo, ht_pwr_lo, hrxc_pwr_lo, hs_pwr_lo, hisn_pwr_lo, lp_pwr_lo, 1'b0);
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mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, ls_pwr_hi, ht_pwr_hi, hrxc_pwr_hi, hs_pwr_hi, hisn_pwr_hi, lp_pwr_hi, 1'b0);
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mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, ls_adc_clk, ht_adc_clk, hrxc_adc_clk, hs_adc_clk, hisn_adc_clk, lp_adc_clk, 1'b0);
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mux8 mux_dbg (major_mode, dbg, lr_dbg, ls_dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, lp_dbg, 1'b0);
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mux8 mux_dbg (major_mode, dbg, lr_dbg, ls_dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, lp_dbg, 1'b0);
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// In all modes, let the ADC's outputs be enabled.
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assign adc_noe = 1'b0;
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@ -39,8 +39,8 @@ reg [2:0] deep_counter;
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reg deep_modulation;
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always @(negedge adc_clk)
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begin
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if(& adc_d[7:6]) after_hysteresis <= 1'b1;
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else if(~(| adc_d[7:4])) after_hysteresis <= 1'b0;
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if(& adc_d[7:6]) after_hysteresis <= 1'b1; // if adc_d >= 196
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else if(~(| adc_d[7:4])) after_hysteresis <= 1'b0; // if adc_d <= 15
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if(~(| adc_d[7:0]))
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begin
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@ -83,20 +83,34 @@ reg [5:0] negedge_cnt;
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reg bit1, bit2, bit3;
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reg [3:0] count_ones;
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reg [3:0] count_zeros;
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wire [7:0] avg;
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reg [7:0] lavg;
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reg signed [12:0] step1;
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reg signed [12:0] step2;
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reg [7:0] stepsize;
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// wire [7:0] avg;
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// reg [7:0] lavg;
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// reg signed [12:0] step1;
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// reg signed [12:0] step2;
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// reg [7:0] stepsize;
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reg [7:0] rx_mod_edge_threshold;
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reg curbit;
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reg [12:0] average;
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wire signed [9:0] dif;
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// reg [12:0] average;
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// wire signed [9:0] dif;
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// storage for two previous samples:
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reg [7:0] adc_d_1;
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reg [7:0] adc_d_2;
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reg [7:0] adc_d_3;
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reg [7:0] adc_d_4;
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// the filtered signal (filter performs noise reduction and edge detection)
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// (gaussian derivative)
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wire signed [10:0] adc_d_filtered;
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assign adc_d_filtered = (adc_d_4 << 1) + adc_d_3 - adc_d_1 - (adc_d << 1);
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// Registers to store steepest edges detected:
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reg [7:0] rx_mod_falling_edge_max;
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reg [7:0] rx_mod_rising_edge_max;
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// A register to send the results to the arm
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reg signed [7:0] to_arm;
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assign avg[7:0] = average[11:4];
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assign dif = lavg - avg;
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reg bit_to_arm;
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reg fdt_indicator, fdt_elapsed;
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@ -115,36 +129,67 @@ reg [2:0] ssp_frame_counter;
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// ADC data appears on the rising edge, so sample it on the falling edge
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always @(negedge adc_clk)
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begin
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// last bit = 0 then fdt = 1172, in case of 0x26 (7-bit command, LSB first!)
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// last bit = 1 then fdt = 1236, in case of 0x52 (7-bit command, LSB first!)
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if(fdt_counter == 11'd740) fdt_indicator = 1'b1;
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// ------------------------------------------------------------------------------------------------------------------------------------------------------------------
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// relevant for TAGSIM_MOD only. Timing of Tag's answer to a command received from a reader
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// ISO14443-3 specifies:
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// fdt = 1172, if last bit was 0.
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// fdt = 1236, if last bit was 1.
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// the FPGA takes care for the 1172 delay. To achieve the additional 1236-1172=64 ticks delay, the ARM must send an additional correction bit (before the start bit).
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// The correction bit will be coded as 00010000, i.e. it adds 4 bits to the transmission stream, causing the required delay.
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if(fdt_counter == 11'd740) fdt_indicator = 1'b1; // fdt_indicator is true for 740 <= fdt_counter <= 1148. Ready to buffer data. (?)
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// Shouldn' this be 1236 - 720 = 516? (The mod_sig_buf can buffer 46 data bits,
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// i.e. a maximum delay of 46 * 16 = 720 adc_clk ticks)
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if(fdt_counter == 11'd1148)
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if(fdt_counter == 11'd1148) // additional 16 (+ eventual n*128) adc_clk_ticks delay will be added by the mod_sig_buf below
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// the remaining 8 ticks delay comes from the 8 ticks timing difference between reseting fdt_counter and the mod_sig_buf clock.
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begin
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if(fdt_elapsed)
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begin
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if(negedge_cnt[3:0] == mod_sig_flip[3:0]) mod_sig_coil <= mod_sig;
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if(negedge_cnt[3:0] == mod_sig_flip[3:0]) mod_sig_coil <= mod_sig; // start modulating (if mod_sig is already set)
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end
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else
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begin
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mod_sig_flip[3:0] <= negedge_cnt[3:0];
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mod_sig_coil <= mod_sig;
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mod_sig_flip[3:0] <= negedge_cnt[3:0]; // exact timing of modulation
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mod_sig_coil <= mod_sig; // modulate (if mod_sig is already set)
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fdt_elapsed = 1'b1;
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fdt_indicator = 1'b0;
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if(~(| mod_sig_ptr[5:0])) mod_sig_ptr <= 6'b001001;
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else temp_buffer_reset = 1'b1; // fix position of the buffer pointer
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if(~(| mod_sig_ptr[5:0])) mod_sig_ptr <= 6'b001001; // didn't receive a 1 yet. Delay next 1 by n*128 ticks.
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else temp_buffer_reset = 1'b1; // else fix the buffer size at current position
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end
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end
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else
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begin
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fdt_counter <= fdt_counter + 1;
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fdt_counter <= fdt_counter + 1; // Count until 1148
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end
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if(& negedge_cnt[3:0])
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//-------------------------------------------------------------------------------------------------------------------------------------------
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// Relevant for READER_LISTEN only
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// look for steepest falling and rising edges:
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if (adc_d_filtered > 0)
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begin
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if (adc_d_filtered > rx_mod_falling_edge_max)
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rx_mod_falling_edge_max <= adc_d_filtered;
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end
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else
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begin
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if (-adc_d_filtered > rx_mod_rising_edge_max)
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rx_mod_rising_edge_max <= -adc_d_filtered;
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end
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// store previous samples for filtering and edge detection:
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adc_d_4 <= adc_d_3;
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adc_d_3 <= adc_d_2;
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adc_d_2 <= adc_d_1;
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adc_d_1 <= adc_d;
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if(& negedge_cnt[3:0]) // == 0xf == 15
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begin
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// When there is a dip in the signal and not in reader mode
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// Relevant for TAGSIM_MOD only (timing Tag's answer. See above)
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// When there is a dip in the signal and not in (READER_MOD, READER_LISTEN, TAGSIM_MOD)
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if(~after_hysteresis && mod_sig_buf_empty && ~((mod_type == 3'b100) || (mod_type == 3'b011) || (mod_type == 3'b010))) // last condition to prevent reset
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begin
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fdt_counter <= 11'd0;
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@ -154,74 +199,33 @@ begin
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mod_sig_ptr <= 6'b000000;
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end
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lavg <= avg;
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if(stepsize<16) stepsize = 8'd16;
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if(dif>0)
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begin
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step1 = dif*3;
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step2 = stepsize*2; // 3:2
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if(step1>step2)
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begin
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curbit = 1'b0;
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stepsize = dif;
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end
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end
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else
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begin
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step1 = dif*3;
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step1 = -step1;
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step2 = stepsize*2;
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if(step1>step2)
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begin
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curbit = 1'b1;
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stepsize = -dif;
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end
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end
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if(curbit)
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begin
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count_zeros <= 4'd0;
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if(& count_ones[3:2])
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begin
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curbit = 1'b0; // suppressed signal
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stepsize = 8'd24; // just a fine number
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end
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// Relevant for READER_LISTEN only
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// detect modulation signal: if modulating, there must be a falling and a rising edge ... and vice versa
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if (rx_mod_falling_edge_max > 6 && rx_mod_rising_edge_max > 6)
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curbit = 1'b1; // modulation
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else
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begin
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count_ones <= count_ones + 1;
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end
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end
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else
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begin
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count_ones <= 4'd0;
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if(& count_zeros[3:0])
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begin
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stepsize = 8'd24;
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end
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else
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begin
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count_zeros <= count_zeros + 1;
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end
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end
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curbit = 1'b0; // no modulation
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// prepare next edge detection:
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rx_mod_rising_edge_max <= 0;
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rx_mod_falling_edge_max <= 0;
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// What do we communicate to the ARM
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if(mod_type == 3'b001) sendbit = after_hysteresis;
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else if(mod_type == 3'b010)
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if(mod_type == 3'b001) sendbit = after_hysteresis; // TAGSIM_LISTEN
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else if(mod_type == 3'b010) // TAGSIM_MOD
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begin
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if(fdt_counter > 11'd772) sendbit = mod_sig_coil;
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else sendbit = fdt_indicator;
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end
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else if(mod_type == 3'b011) sendbit = curbit;
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else sendbit = 1'b0;
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else if(mod_type == 3'b011) sendbit = curbit; // READER_LISTEN
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else sendbit = 1'b0; // READER_MOD, SNIFFER
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end
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if(~(| negedge_cnt[3:0])) average <= adc_d;
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else average <= average + adc_d;
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if(negedge_cnt == 7'd63)
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//------------------------------------------------------------------------------------------------------------------------------------------
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// Relevant for SNIFFER mode only. Prepare communication to ARM.
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if(negedge_cnt == 7'd63)
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begin
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if(deep_modulation)
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begin
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@ -234,7 +238,7 @@ begin
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negedge_cnt <= 0;
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end
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end
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else
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begin
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negedge_cnt <= negedge_cnt + 1;
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@ -256,35 +260,48 @@ begin
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bit3 <= curbit;
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end
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if(mod_type != 3'b000)
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//--------------------------------------------------------------------------------------------------------------------------------------------------------------
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// Relevant in TAGSIM_MOD only. Delay-Line to buffer data and send it at the correct time
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// Note: Data in READER_MOD is fed through this delay line as well.
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if(mod_type != 3'b000) // != SNIFFER
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begin
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if(negedge_cnt[3:0] == 4'b1000)
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if(negedge_cnt[3:0] == 4'b1000) // == 0x8
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begin
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// The modulation signal of the tag
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||||
mod_sig_buf[47:0] <= {mod_sig_buf[46:1], ssp_dout, 1'b0};
|
||||
if((ssp_dout || (| mod_sig_ptr[5:0])) && ~fdt_elapsed)
|
||||
if(mod_sig_ptr == 6'b101110)
|
||||
// The modulation signal of the tag. The delay line is only relevant for TAGSIM_MOD, but used in other modes as well.
|
||||
// Note: this means that even in READER_MOD, there will be an arbitrary delay depending on the time of a previous reset of fdt_counter and the time and
|
||||
// content of the next bit to be transmitted.
|
||||
mod_sig_buf[47:0] <= {mod_sig_buf[46:1], ssp_dout, 1'b0}; // shift in new data starting at mod_sig_buf[1]. mod_sig_buf[0] = 0 always.
|
||||
if((ssp_dout || (| mod_sig_ptr[5:0])) && ~fdt_elapsed) // buffer a 1 (and all subsequent data) until fdt_counter = 1148 adc_clk ticks.
|
||||
if(mod_sig_ptr == 6'b101110) // buffer overflow at 46 - this would mean data loss
|
||||
begin
|
||||
mod_sig_ptr <= 6'b000000;
|
||||
end
|
||||
else mod_sig_ptr <= mod_sig_ptr + 1;
|
||||
else if(fdt_elapsed && ~temp_buffer_reset)
|
||||
else mod_sig_ptr <= mod_sig_ptr + 1; // increase buffer (= increase delay by 16 adc_clk ticks). ptr always points to first 1.
|
||||
else if(fdt_elapsed && ~temp_buffer_reset)
|
||||
// fdt_elapsed. If we didn't receive a 1 yet, ptr will be at 9 and not yet fixed. Otherwise temp_buffer_reset will be 1 already.
|
||||
begin
|
||||
if(ssp_dout) temp_buffer_reset = 1'b1;
|
||||
if(mod_sig_ptr == 6'b000010) mod_sig_ptr <= 6'b001001;
|
||||
else mod_sig_ptr <= mod_sig_ptr - 1;
|
||||
// wait for the next 1 after fdt_elapsed before fixing the delay and starting modulation. This ensures that the response can only happen
|
||||
// at intervals of 8 * 16 = 128 adc_clk ticks intervals (as defined in ISO14443-3)
|
||||
if(ssp_dout) temp_buffer_reset = 1'b1;
|
||||
if(mod_sig_ptr == 6'b000010) mod_sig_ptr <= 6'b001001; // still nothing received, need to go for the next interval
|
||||
else mod_sig_ptr <= mod_sig_ptr - 1; // decrease buffer.
|
||||
end
|
||||
else
|
||||
// mod_sig_ptr and therefore the delay is now fixed until fdt_counter is reset (this can happen in SNIFFER and TAGSIM_LISTEN mode only. Note that SNIFFER
|
||||
// mode (3'b000) is the default and is active in FPGA_MAJOR_MODE_OFF if no other minor mode is explicitly requested.
|
||||
begin
|
||||
// side effect: when ptr = 1 it will cancel the first 1 of every block of ones
|
||||
// don't modulate with the correction bit (which is sent as 00010000, all other bits will come with at least 2 consecutive 1s)
|
||||
// side effect: when ptr = 1 it will cancel the first 1 of every block of ones. Note: this would only be the case if we received a 1 just before fdt_elapsed.
|
||||
if(~mod_sig_buf[mod_sig_ptr-1] && ~mod_sig_buf[mod_sig_ptr+1]) mod_sig = 1'b0;
|
||||
else mod_sig = mod_sig_buf[mod_sig_ptr] & fdt_elapsed; // & fdt_elapsed was for direct relay to oe4
|
||||
// finally, do the modulation:
|
||||
else mod_sig = mod_sig_buf[mod_sig_ptr] & fdt_elapsed;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// SSP Clock and data
|
||||
//-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
// Communication to ARM (SSP Clock and data)
|
||||
// SNIFFER mode (ssp_clk = adc_clk / 8, ssp_frame clock = adc_clk / 64)):
|
||||
if(mod_type == 3'b000)
|
||||
begin
|
||||
if(negedge_cnt[2:0] == 3'b100)
|
||||
|
|
@ -308,6 +325,9 @@ begin
|
|||
bit_to_arm = to_arm[7];
|
||||
end
|
||||
else
|
||||
//-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
// Communication to ARM (SSP Clock and data)
|
||||
// all other modes (ssp_clk = adc_clk / 16, ssp_frame clock = adc_clk / 128):
|
||||
begin
|
||||
if(negedge_cnt[3:0] == 4'b1000) ssp_clk <= 1'b0;
|
||||
|
||||
|
|
@ -331,30 +351,29 @@ end
|
|||
|
||||
assign ssp_din = bit_to_arm;
|
||||
|
||||
// Modulating carrier frequency is fc/16
|
||||
|
||||
// Modulating carrier (adc_clk/16, for TAGSIM_MOD only). Will be 0 for other modes.
|
||||
wire modulating_carrier;
|
||||
assign modulating_carrier = (mod_sig_coil & negedge_cnt[3] & (mod_type == 3'b010));
|
||||
assign pwr_hi = (ck_1356megb & (((mod_type == 3'b100) & ~mod_sig_coil) || (mod_type == 3'b011)));
|
||||
assign modulating_carrier = (mod_sig_coil & negedge_cnt[3] & (mod_type == 3'b010)); // in TAGSIM_MOD only. Otherwise always 0.
|
||||
|
||||
// This one is all LF, so doesn't matter
|
||||
//assign pwr_oe2 = modulating_carrier;
|
||||
assign pwr_oe2 = 1'b0;
|
||||
// for READER_MOD only: drop carrier for mod_sig_coil==1 (pause), READER_LISTEN: carrier always on, others: carrier always off
|
||||
assign pwr_hi = (ck_1356megb & (((mod_type == 3'b100) & ~mod_sig_coil) || (mod_type == 3'b011)));
|
||||
|
||||
// Toggle only one of these, since we are already producing much deeper
|
||||
// modulation than a real tag would.
|
||||
//assign pwr_oe1 = modulating_carrier;
|
||||
|
||||
// Enable HF antenna drivers:
|
||||
assign pwr_oe1 = 1'b0;
|
||||
assign pwr_oe4 = modulating_carrier;
|
||||
//assign pwr_oe4 = 1'b0;
|
||||
|
||||
// This one is always on, so that we can watch the carrier.
|
||||
//assign pwr_oe3 = modulating_carrier;
|
||||
assign pwr_oe3 = 1'b0;
|
||||
|
||||
// TAGSIM_MOD: short circuit antenna with different resistances (modulated by modulating_carrier)
|
||||
// for pwr_oe4 = 1 (tristate): antenna load = 10k || 33 = 32,9 Ohms
|
||||
// for pwr_oe4 = 0 (active): antenna load = 10k || 33 || 33 = 16,5 Ohms
|
||||
assign pwr_oe4 = modulating_carrier;
|
||||
|
||||
// This is all LF, so doesn't matter.
|
||||
assign pwr_oe2 = 1'b0;
|
||||
assign pwr_lo = 1'b0;
|
||||
|
||||
|
||||
assign dbg = negedge_cnt[3];
|
||||
|
||||
// Unused.
|
||||
assign pwr_lo = 1'b0;
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
run -ifn fpga.v -ifmt Verilog -ofn fpga.ngc -ofmt NGC -p xc2s30-6vq100 -opt_mode Speed -opt_level 1 -ent fpga
|
||||
run -ifn fpga.v -ifmt Verilog -ofn fpga.ngc -ofmt NGC -p xc2s30-5-vq100 -opt_mode Speed -opt_level 1 -ent fpga
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue