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FPGA Hi-Simulate: Added 212kHz SSP-Clock option

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AntiCat 2018-09-05 22:23:23 +02:00
commit e472a21194
2 changed files with 5 additions and 2 deletions
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fpga/fpga_hf.bit
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fpga/hi_simulate.v
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@ -65,9 +65,12 @@ begin
if(mod_type == 3'b101) if(mod_type == 3'b101)
// Get bit every at 53KHz (every 8th carrier bit of 424kHz) // Get bit every at 53KHz (every 8th carrier bit of 424kHz)
ssp_clk <= ssp_clk_divider[7]; ssp_clk <= ssp_clk_divider[7];
else if(mod_type == 3'b010)
// Get next bit at 212kHz
ssp_clk <= ssp_clk_divider[5];
else else
// Get next bit at 424Khz // Get next bit at 424Khz
ssp_clk <= ssp_clk_divider[4] ssp_clk <= ssp_clk_divider[4];
end end
@ -121,6 +124,6 @@ assign pwr_oe4 = modulating_carrier;
// This one is always on, so that we can watch the carrier. // This one is always on, so that we can watch the carrier.
assign pwr_oe3 = 1'b0; assign pwr_oe3 = 1'b0;
assign dbg = modulating_carrier; assign dbg = ssp_din;
endmodule endmodule