diff --git a/armsrc/fpgaloader.c b/armsrc/fpgaloader.c index f1f157eec..8313404bf 100644 --- a/armsrc/fpgaloader.c +++ b/armsrc/fpgaloader.c @@ -134,7 +134,7 @@ void SetupSpi(int mode) { // Set up the synchronous serial port with the set of options that fits // the FPGA mode. Both RX and TX are always enabled. //----------------------------------------------------------------------------- -void FpgaSetupSsc(void) { +void FpgaSetupSsc(uint16_t fpga_mode) { // First configure the GPIOs, and get ourselves a clock. AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_FRAME | @@ -152,12 +152,16 @@ void FpgaSetupSsc(void) { // data and frame signal is sampled on falling edge of RK AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1); - // 8 bits per transfer, no loopback, MSB first, 1 transfer per sync + // 8, 16 or 32 bits per transfer, no loopback, MSB first, 1 transfer per sync // pulse, no output sync - AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) | AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0); + if ((fpga_mode & FPGA_MAJOR_MODE_MASK) == FPGA_MAJOR_MODE_HF_READER && FpgaGetCurrent() == FPGA_BITSTREAM_HF) { + AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(16) | AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0); + } else { + AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) | AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0); + } - // TX clock comes from TK pin, no clock output, outputs change on falling - // edge of TK, frame sync is sampled on rising edge of TK, start TX on rising edge of TF + // TX clock comes from TK pin, no clock output, outputs change on rising edge of TK, + // TF (frame sync) is sampled on falling edge of TK, start TX on rising edge of TF AT91C_BASE_SSC->SSC_TCMR = SSC_CLOCK_MODE_SELECT(2) | SSC_CLOCK_MODE_START(5); // tx framing is the same as the rx framing @@ -171,7 +175,7 @@ void FpgaSetupSsc(void) { // a single buffer as a circular buffer (so that we just chain back to // ourselves, not to another buffer). //----------------------------------------------------------------------------- -bool FpgaSetupSscDma(uint8_t *buf, int len) { +bool FpgaSetupSscDma(uint8_t *buf, uint16_t len) { if (buf == NULL) return false; FpgaDisableSscDma(); @@ -439,7 +443,7 @@ void FpgaDownloadAndGo(int bitstream_version) { // The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 // where C is the 4 bit command and D is the 12 bit data // -// @params cmd and v gets or over eachother. Take careful note of overlapping bits. +// @params cmd and v gets OR:ED over each other. Take careful note of overlapping bits. //----------------------------------------------------------------------------- void FpgaSendCommand(uint16_t cmd, uint16_t v) { SetupSpi(SPI_FPGA_MODE); diff --git a/armsrc/fpgaloader.h b/armsrc/fpgaloader.h index 636c5b7b7..474c08e1a 100644 --- a/armsrc/fpgaloader.h +++ b/armsrc/fpgaloader.h @@ -52,23 +52,26 @@ thres| x x x x x x x x #define FPGA_CMD_TRACE_ENABLE (2<<12) // C // Definitions for the FPGA configuration word. +#define FPGA_MAJOR_MODE_MASK 0x01C0 +#define FPGA_MINOR_MODE_MASK 0x003F + // LF -#define FPGA_MAJOR_MODE_LF_READER (0<<5) -#define FPGA_MAJOR_MODE_LF_EDGE_DETECT (1<<5) -#define FPGA_MAJOR_MODE_LF_PASSTHRU (2<<5) -#define FPGA_MAJOR_MODE_LF_ADC (3<<5) +#define FPGA_MAJOR_MODE_LF_READER (0<<6) +#define FPGA_MAJOR_MODE_LF_EDGE_DETECT (1<<6) +#define FPGA_MAJOR_MODE_LF_PASSTHRU (2<<6) +#define FPGA_MAJOR_MODE_LF_ADC (3<<6) // HF -#define FPGA_MAJOR_MODE_HF_READER_TX (0<<5) // D -#define FPGA_MAJOR_MODE_HF_READER_RX_XCORR (1<<5) // D -#define FPGA_MAJOR_MODE_HF_SIMULATOR (2<<5) // D -#define FPGA_MAJOR_MODE_HF_ISO14443A (3<<5) // D -#define FPGA_MAJOR_MODE_HF_SNOOP (4<<5) // D -#define FPGA_MAJOR_MODE_HF_ISO18092 (5<<5) // D -#define FPGA_MAJOR_MODE_HF_GET_TRACE (6<<5) // D +#define FPGA_MAJOR_MODE_HF_READER (0<<6) // D +#define FPGA_MAJOR_MODE_HF_SIMULATOR (1<<6) // D +#define FPGA_MAJOR_MODE_HF_ISO14443A (2<<6) // D +#define FPGA_MAJOR_MODE_HF_SNOOP (3<<6) // D +#define FPGA_MAJOR_MODE_HF_ISO18092 (4<<6) // D +#define FPGA_MAJOR_MODE_HF_GET_TRACE (5<<6) // D // BOTH HF / LF -#define FPGA_MAJOR_MODE_OFF (7<<5) // D +#define FPGA_MAJOR_MODE_OFF (7<<6) // D + // Options for LF_READER #define FPGA_LF_ADC_READER_FIELD 0x1 @@ -78,13 +81,20 @@ thres| x x x x x x x x #define FPGA_LF_EDGE_DETECT_READER_FIELD 0x1 #define FPGA_LF_EDGE_DETECT_TOGGLE_MODE 0x2 -// Options for the HF reader, tx to tag -#define FPGA_HF_READER_TX_SHALLOW_MOD 0x1 +// Options for the HF reader +#define FPGA_HF_READER_MODE_RECEIVE_IQ (0<<0) +#define FPGA_HF_READER_MODE_RECEIVE_AMPLITUDE (1<<0) +#define FPGA_HF_READER_MODE_RECEIVE_PHASE (2<<0) +#define FPGA_HF_READER_MODE_SEND_FULL_MOD (3<<0) +#define FPGA_HF_READER_MODE_SEND_SHALLOW_MOD (4<<0) +#define FPGA_HF_READER_MODE_SNOOP_IQ (5<<0) +#define FPGA_HF_READER_MODE_SNOOP_AMPLITUDE (6<<0) +#define FPGA_HF_READER_MODE_SNOOP_PHASE (7<<0) +#define FPGA_HF_READER_MODE_SEND_JAM (8<<0) -// Options for the HF reader, correlating against rx from tag -#define FPGA_HF_READER_RX_XCORR_848_KHZ 0x1 -#define FPGA_HF_READER_RX_XCORR_SNOOP 0x2 -#define FPGA_HF_READER_RX_XCORR_QUARTER 0x4 +#define FPGA_HF_READER_SUBCARRIER_848_KHZ (0<<4) +#define FPGA_HF_READER_SUBCARRIER_424_KHZ (1<<4) +#define FPGA_HF_READER_SUBCARRIER_212_KHZ (2<<4) // Options for the HF simulated tag, how to modulate #define FPGA_HF_SIMULATOR_NO_MODULATION 0x0 // 0000 @@ -112,9 +122,9 @@ void FpgaEnableTracing(void); void FpgaDisableTracing(void); void FpgaDownloadAndGo(int bitstream_version); // void FpgaGatherVersion(int bitstream_version, char *dst, int len); -void FpgaSetupSsc(void); +void FpgaSetupSsc(uint16_t fpga_mode); void SetupSpi(int mode); -bool FpgaSetupSscDma(uint8_t *buf, int len); +bool FpgaSetupSscDma(uint8_t *buf, uint16_t len); void Fpga_print_status(void); int FpgaGetCurrent(void); void SetAdcMuxFor(uint32_t whichGpio);