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chg: 'lf cmdread' - adjusting loop
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1 changed files with 45 additions and 51 deletions
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@ -26,6 +26,32 @@
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# define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
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# define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
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#endif
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#endif
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#define START_GAP 31*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (15fc)
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#define WRITE_GAP 20*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (10fc)
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#define WRITE_0 18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (24fc)
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#define WRITE_1 50*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (56fc) 432 for T55x7; 448 for E5550
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#define READ_GAP 15*8
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// VALUES TAKEN FROM EM4x function: SendForward
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// START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
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// WRITE_GAP = 128; (16*8)
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// WRITE_1 = 256 32*8; (32*8)
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// These timings work for 4469/4269/4305 (with the 55*8 above)
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// WRITE_0 = 23*8 , 9*8
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// Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
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// TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
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// Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
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// T0 = TIMER_CLOCK1 / 125000 = 192
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// 1 Cycle = 8 microseconds(us) == 1 field clock
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// new timer:
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// = 1us = 1.5ticks
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// 1fc = 8us = 12ticks
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/**
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/**
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* Function to do a modulation and then get samples.
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* Function to do a modulation and then get samples.
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* @param delay_off
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* @param delay_off
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@ -33,13 +59,7 @@
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* @param useHighFreg
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* @param useHighFreg
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* @param command
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* @param command
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*/
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*/
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void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t periods, uint32_t useHighFreq, uint8_t *command)
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void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t periods, uint32_t useHighFreq, uint8_t *command) {
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{
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/* Make sure the tag is reset */
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FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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SpinDelay(200);
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uint16_t period_0 = periods >> 16;
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uint16_t period_0 = periods >> 16;
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uint16_t period_1 = periods & 0xFFFF;
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uint16_t period_1 = periods & 0xFFFF;
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@ -53,33 +73,30 @@ void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t periods, uint3
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LFSetupFPGAForADC(sc.divisor, 1);
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LFSetupFPGAForADC(sc.divisor, 1);
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// And a little more time for the tag to fully power up
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// Trigger T55x7 in mode.
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SpinDelay(50);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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WaitUS(START_GAP);
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// now modulate the reader field
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// now modulate the reader field
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while(*command != '\0' && *command != ' ') {
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while (*command != '\0' && *command != ' ') {
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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LED_D_OFF();
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WaitUS(delay_off);
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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LED_D_ON();
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LED_D_ON();
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if(*(command++) == '0')
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if (*(command++) == '0')
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WaitUS(period_0);
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TurnReadLFOn(period_0);
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else
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else
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WaitUS(period_1);
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TurnReadLFOn(period_1);
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LED_D_OFF();
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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WaitUS(delay_off);
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}
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}
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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LED_D_OFF();
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WaitUS(delay_off);
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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// now do the read
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// now do the read
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DoAcquisition_config(false, 0);
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DoAcquisition_config(false, 0);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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cmd_send(CMD_ACK,0,0,0,0,0);
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}
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}
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/* blank r/w tag data stream
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/* blank r/w tag data stream
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@ -1171,29 +1188,6 @@ void CmdIOdemodFSK(int findone, uint32_t *high, uint32_t *low, int ledcontrol) {
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* Q5 tags seems to have issues when these values changes.
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* Q5 tags seems to have issues when these values changes.
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*/
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*/
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#define START_GAP 31*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (15fc)
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#define WRITE_GAP 20*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (10fc)
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#define WRITE_0 18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (24fc)
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#define WRITE_1 50*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (56fc) 432 for T55x7; 448 for E5550
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#define READ_GAP 15*8
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// VALUES TAKEN FROM EM4x function: SendForward
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// START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
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// WRITE_GAP = 128; (16*8)
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// WRITE_1 = 256 32*8; (32*8)
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// These timings work for 4469/4269/4305 (with the 55*8 above)
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// WRITE_0 = 23*8 , 9*8
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// Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
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// TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
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// Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
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// T0 = TIMER_CLOCK1 / 125000 = 192
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// 1 Cycle = 8 microseconds(us) == 1 field clock
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// new timer:
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// = 1us = 1.5ticks
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// 1fc = 8us = 12ticks
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void TurnReadLFOn(uint32_t delay) {
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void TurnReadLFOn(uint32_t delay) {
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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