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Make detection threshold for ISO14443A configurable

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This adds a new command "hw sethfthresh" to configure the thresholds
used inside the FPGA while demodulating ISO14443A. The thresholds
need to be increased on particularly noisy hardware, such as certain
Chinese PM3 Easy clones.
This commit is contained in:
Christian Zietz 2024-02-01 17:48:06 +01:00
commit dbfd8b7a6d
12 changed files with 68 additions and 12 deletions
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3
fpga/define.v
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@ -39,7 +39,8 @@
+-------------------------------------------------+
| C C C C M M M P P P P P P | C = FPGA_CMD_SET_CONFREG, M = FPGA_MAJOR_MODE_*, P = FPGA_LF_* or FPGA_HF_* parameter
| C C C C D D D D D D D D | C = FPGA_CMD_SET_DIVISOR, D = divisor
| C C C C T T T T T T T T | C = FPGA_CMD_SET_EDGE_DETECT_THRESHOLD, T = threshold
| C C C C T T T T T T T T | C = FPGA_CMD_SET_EDGE_DETECT_THRESHOLD, T = threshold (in LF mode)
| C C C C H H H H H H T T T T T T | C = FPGA_CMD_SET_EDGE_DETECT_THRESHOLD, H = threshold_high, T = threshold (in HF/14a mode)
| C C C C E | C = FPGA_CMD_TRACE_ENABLE, E=0 off, E=1 on
+-------------------------------------------------+

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fpga/fpga_icopyx_hf.bit
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8
fpga/fpga_icopyx_hf.v
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@ -127,6 +127,10 @@ hi_simulate hs(
);
// 2 - HF ISO14443-A
`define EDGE_DETECT_THRESHOLD 3
`define EDGE_DETECT_THRESHOLDHIGH 20
hi_iso14443a hisn(
.ck_1356meg (ck_1356meg),
.pwr_lo (hisn_pwr_lo),
@ -142,7 +146,9 @@ hi_iso14443a hisn(
.ssp_dout (ssp_dout),
.ssp_clk (hisn_ssp_clk),
.debug (hisn_debug),
.mod_type (minor_mode)
.mod_type (minor_mode),
.edge_detect_threshold (`EDGE_DETECT_THRESHOLD),
.edge_detect_threshold_high (`EDGE_DETECT_THRESHOLDHIGH)
);
// 3 - HF sniff

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fpga/fpga_pm3_felica.bit
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BIN
fpga/fpga_pm3_hf.bit
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fpga/fpga_pm3_hf_15.bit
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fpga/fpga_pm3_lf.bit
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17
fpga/fpga_pm3_top.v
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@ -111,6 +111,8 @@ always @(posedge spck) if (~ncs) shift_reg <= {shift_reg[14:0], mosi};
reg trace_enable;
reg [7:0] lf_ed_threshold;
reg [10:0] hf_edge_detect_threshold;
reg [10:0] hf_edge_detect_threshold_high;
// adjustable frequency clock
wire [7:0] pck_cnt;
@ -124,6 +126,12 @@ reg [11:0] conf_word;
reg [8:0] conf_word;
`endif
initial
begin
hf_edge_detect_threshold <= 7;
hf_edge_detect_threshold_high <= 20;
end
// We switch modes between transmitting to the 13.56 MHz tag and receiving
// from it, which means that we must make sure that we can do so without
// glitching, or else we will glitch the transmitted carrier.
@ -147,6 +155,11 @@ begin
`else
`FPGA_CMD_SET_CONFREG: conf_word <= shift_reg[8:0];
`FPGA_CMD_TRACE_ENABLE: trace_enable <= shift_reg[0];
`FPGA_CMD_SET_EDGE_DETECT_THRESHOLD:
begin
hf_edge_detect_threshold <= {6'b0, shift_reg[5:0]};
hf_edge_detect_threshold_high <= {6'b0, shift_reg[11:6]};
end
`endif
endcase
end
@ -321,7 +334,9 @@ hi_iso14443a hisn(
.pwr_oe2 (mux2_pwr_oe2),
.pwr_oe3 (mux2_pwr_oe3),
.pwr_oe4 (mux2_pwr_oe4),
.debug (mux2_debug)
.debug (mux2_debug),
.edge_detect_threshold (hf_edge_detect_threshold),
.edge_detect_threshold_high (hf_edge_detect_threshold_high)
);
`endif // WITH_HF2

13
fpga/hi_iso14443a.v
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@ -19,6 +19,8 @@ module hi_iso14443a(
input ck_1356meg,
input [7:0] adc_d,
input [3:0] mod_type,
input [10:0] edge_detect_threshold,
input [10:0] edge_detect_threshold_high,
input ssp_dout,
output ssp_din,
@ -212,13 +214,6 @@ reg signed [10:0] rx_mod_falling_edge_max;
reg signed [10:0] rx_mod_rising_edge_max;
reg curbit;
`ifdef PM3ICOPYX
`define EDGE_DETECT_THRESHOLD 3
`else
`define EDGE_DETECT_THRESHOLD 7
`endif
`define EDGE_DETECT_THRESHOLDHIGH 20
always @(negedge adc_clk)
begin
if(negedge_cnt[3:0] == mod_detect_reset_time)
@ -226,7 +221,7 @@ begin
if (mod_type == `FPGA_HF_ISO14443A_SNIFFER)
begin
// detect modulation signal: if modulating, there must have been a falling AND a rising edge
if ((rx_mod_falling_edge_max > `EDGE_DETECT_THRESHOLDHIGH) && (rx_mod_rising_edge_max < -`EDGE_DETECT_THRESHOLDHIGH))
if ((rx_mod_falling_edge_max > edge_detect_threshold_high) && (rx_mod_rising_edge_max < -edge_detect_threshold_high))
curbit <= 1'b1; // modulation
else
curbit <= 1'b0; // no modulation
@ -234,7 +229,7 @@ begin
else
begin
// detect modulation signal: if modulating, there must have been a falling AND a rising edge
if ((rx_mod_falling_edge_max > `EDGE_DETECT_THRESHOLD) && (rx_mod_rising_edge_max < -`EDGE_DETECT_THRESHOLD))
if ((rx_mod_falling_edge_max > edge_detect_threshold) && (rx_mod_rising_edge_max < -edge_detect_threshold))
curbit <= 1'b1; // modulation
else
curbit <= 1'b0; // no modulation