MAJOR update, added hitag2 reader, emulation and eavesdropping, lots of new code, including FPGA tweaks, part 2

fpga/Makefile

@@ -6,7 +6,7 @@ clean:
 	$(DELETE) fpga.map  fpga.ngc           fpga_ngdbuild.xrpt  fpga.pcf         fpga-placed_pad.csv  fpga-placed.ptwx      fpga.rbt          xlnx_auto_0_xdb
 	$(DELETE) fpga.bld  fpga.mrp  fpga.ngc_xst.xrpt  fpga.ngm            fpga-placed.ncd  fpga-placed_pad.txt  fpga-placed.unroutes  fpga_summary.xml  netlist.lst     xst
 
-fpga.ngc: fpga.v fpga.ucf xst.scr util.v lo_simulate.v lo_read.v lo_passthru.v hi_simulate.v hi_read_tx.v hi_read_rx_xcorr.v hi_iso14443a.v
+fpga.ngc: fpga.v fpga.ucf xst.scr util.v lo_edge_detect.v lo_read.v lo_passthru.v hi_simulate.v hi_read_tx.v hi_read_rx_xcorr.v hi_iso14443a.v
 	$(DELETE) fpga.ngc
 	$(XILINX_TOOLS_PREFIX)xst -ifn xst.scr
 

fpga/fpga.v

@@ -14,7 +14,7 @@
 
 `include "lo_read.v"
 `include "lo_passthru.v"
-`include "lo_simulate.v"
+`include "lo_edge_detect.v"
 `include "hi_read_tx.v"
 `include "hi_read_rx_xcorr.v"
 `include "hi_simulate.v"
@@ -111,6 +111,10 @@ assign hi_read_rx_xcorr_quarter = conf_word[2];
 wire [2:0] hi_simulate_mod_type;
 assign hi_simulate_mod_type = conf_word[2:0];
 
+// For the high-frequency simulated tag: what kind of modulation to use.
+wire lf_field;
+assign lf_field = conf_word[0];
+
 //-----------------------------------------------------------------------------
 // And then we instantiate the modules corresponding to each of the FPGA's
 // major modes, and use muxes to connect the outputs of the active mode to
@@ -136,13 +140,14 @@ lo_passthru lp(
 	lp_dbg, divisor
 );
 
-lo_simulate ls(
+lo_edge_detect ls(
 	pck0, ck_1356meg, ck_1356megb,
 	ls_pwr_lo, ls_pwr_hi, ls_pwr_oe1, ls_pwr_oe2, ls_pwr_oe3, ls_pwr_oe4,
 	adc_d, ls_adc_clk,
 	ls_ssp_frame, ls_ssp_din, ssp_dout, ls_ssp_clk,
 	cross_hi, cross_lo,
-	ls_dbg, divisor
+	ls_dbg, divisor,
+	lf_field
 );
 
 hi_read_tx ht(

fpga/lo_edge_detect.v

@@ -0,0 +1,90 @@
+//-----------------------------------------------------------------------------
+// The way that we connect things in low-frequency simulation mode. In this
+// case just pass everything through to the ARM, which can bit-bang this
+// (because it is so slow).
+//
+// Jonathan Westhues, April 2006
+//-----------------------------------------------------------------------------
+
+module lo_edge_detect(
+    pck0, ck_1356meg, ck_1356megb,
+    pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
+    adc_d, adc_clk,
+    ssp_frame, ssp_din, ssp_dout, ssp_clk,
+    cross_hi, cross_lo,
+    dbg,
+	  divisor,
+		lf_field
+);
+    input pck0, ck_1356meg, ck_1356megb;
+    output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
+    input [7:0] adc_d;
+    output adc_clk;
+    input ssp_dout;
+    output ssp_frame, ssp_din, ssp_clk;
+    input cross_hi, cross_lo;
+    output dbg;
+	  input [7:0] divisor;
+		input lf_field;
+
+// Divide the clock to be used for the ADC
+reg [7:0] pck_divider;
+reg clk_state;
+
+wire tag_modulation; 
+assign tag_modulation = ssp_dout & !lf_field;
+wire reader_modulation; 
+assign reader_modulation = !ssp_dout & lf_field & clk_state;
+
+// No logic, straight through.
+assign pwr_oe1 = 1'b0; // not used in LF mode
+assign pwr_oe2 = tag_modulation;
+assign pwr_oe3 = tag_modulation;
+assign pwr_oe4 = tag_modulation;
+assign ssp_clk = cross_lo;
+assign pwr_lo = reader_modulation;
+assign pwr_hi = 1'b0;
+assign dbg = ssp_frame;
+
+always @(posedge pck0)
+begin
+	if(pck_divider == divisor[7:0])
+		begin
+			pck_divider <= 8'd0;
+			clk_state = !clk_state;
+		end
+	else
+	begin
+		pck_divider <= pck_divider + 1;
+	end
+end
+
+assign adc_clk = ~clk_state;
+
+// Toggle the output with hysteresis
+//  Set to high if the ADC value is above 200
+//  Set to low if the ADC value is below 64
+reg is_high;
+reg is_low;
+reg output_state;
+
+always @(posedge pck0)
+begin
+	if((pck_divider == 8'd7) && !clk_state) begin
+		is_high = (adc_d >= 8'd190);
+		is_low = (adc_d <= 8'd70);
+	end
+end
+
+always @(posedge is_high or posedge is_low)
+begin
+	if(is_high)
+		output_state <= 1'd1;
+	else if(is_low)
+		output_state <= 1'd0;
+end
+
+assign ssp_frame = output_state;
+
+endmodule
+