mirror of
https://github.com/RfidResearchGroup/proxmark3.git
synced 2025-08-14 18:48:13 -07:00
Merge branch 'master' into feature/iso15693-standalone
This commit is contained in:
Iceman
GitHub
commit
d0f2f6622b
31 changed files with 352 additions and 299 deletions
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@ -1257,8 +1257,8 @@ static void PacketReceived(PacketCommandNG *packet) {
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uint8_t pwd[4];
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} PACKED;
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struct p *payload = (struct p *) packet->data.asBytes;
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DisablePrivacySlixLIso15693(payload->pwd);
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break;
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DisablePrivacySlixLIso15693(payload->pwd);
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break;
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}
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#endif
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@ -1317,8 +1317,8 @@ static void PacketReceived(PacketCommandNG *packet) {
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SimulateIso14443bTag(packet->data.asBytes);
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break;
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}
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case CMD_HF_ISO14443B_COMMAND: {
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iso14b_raw_cmd_t *payload = (iso14b_raw_cmd_t*)packet->data.asBytes;
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case CMD_HF_ISO14443B_COMMAND: {
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iso14b_raw_cmd_t *payload = (iso14b_raw_cmd_t *)packet->data.asBytes;
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SendRawCommand14443B_Ex(payload);
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break;
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}
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@ -1704,14 +1704,14 @@ static void PacketReceived(PacketCommandNG *packet) {
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break;
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}
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case CMD_HF_ICLASS_CHKKEYS: {
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iClass_Authentication_fast((iclass_chk_t*)packet->data.asBytes);
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iClass_Authentication_fast((iclass_chk_t *)packet->data.asBytes);
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break;
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}
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case CMD_HF_ICLASS_DUMP: {
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iClass_Dump(packet->data.asBytes);
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break;
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}
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case CMD_HF_ICLASS_RESTORE: {
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case CMD_HF_ICLASS_RESTORE: {
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iClass_Restore((iclass_restore_req_t *)packet->data.asBytes);
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break;
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}
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@ -1546,7 +1546,7 @@ void iClass_Authentication_fast(iclass_chk_t *p) {
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Iso15693InitReader();
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bool isOK = false;
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uint32_t start_time = 0, eof_time = 0;
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if (select_iclass_tag(&hdr, p->use_credit_key, &eof_time) == false)
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goto out;
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@ -2671,7 +2671,7 @@ int iso14443a_select_card(uint8_t *uid_ptr, iso14a_card_select_t *p_card, uint32
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} // else force RATS
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if ((sak & 0x20) == 0) Dbprintf("Forcing RATS according to hf 14a config");
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// RATS, Request for answer to select
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if (no_rats == false) {
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uint8_t rats[] = { ISO14443A_CMD_RATS, 0x80, 0x00, 0x00 }; // FSD=256, FSDI=8, CID=0
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@ -26,12 +26,12 @@
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#include "ticks.h"
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#include "iso14b.h" // defines for ETU conversions
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/*
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/*
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* Current timing issues with ISO14443-b implementation
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* Proxmark3
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* Carrier Frequency 13.56MHz
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* Proxmark3
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* Carrier Frequency 13.56MHz
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* SSP_CLK runs at 13.56MHz / 4 = 3,39MHz
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*
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*
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*
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* PROBLEM 1.
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* ----------
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@ -62,7 +62,7 @@
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#define DELAY_ARM_TO_TAG 16
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#define DELAY_TAG_TO_ARM 32
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// SSP_CLK runs at 13.56MHz / 4 = 3,39MHz when sniffing.
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// SSP_CLK runs at 13.56MHz / 4 = 3,39MHz when sniffing.
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// All values should be multiples of 16
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#define DELAY_TAG_TO_ARM_SNIFF 32
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#define DELAY_READER_TO_ARM_SNIFF 32
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@ -86,7 +86,7 @@
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*
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* FWI_max == 2^14 = 16384
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* FWT(max) = (256 x 16 / fc) * 16384 == 4949
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*
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*
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* Which gives a maximum Frame Waiting time of FWT(max) == 4949 ms
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* FWT(max) in ETU 4949000 / 9.4395 µS = 524286 ETU
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*
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@ -106,12 +106,12 @@
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// Activation frame waiting time
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// 512 ETU?
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// 65536/fc == 4833 µS or 4.833ms
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// SSP_CLK = 4833 µS * 3.39 = 16384
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// SSP_CLK = 4833 µS * 3.39 = 16384
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#ifndef FWT_TIMEOUT_14B
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# define FWT_TIMEOUT_14B (16384)
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#endif
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#endif
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// ETU 14 * 9.4395 µS = 132 µS == 0.132ms
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// ETU 14 * 9.4395 µS = 132 µS == 0.132ms
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// TR2, counting from start of PICC EOF 14 ETU.
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#define DELAY_ISO14443B_PICC_TO_PCD_READER ETU_TO_SSP(14)
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#define DELAY_ISO14443B_PCD_TO_PICC_READER ETU_TO_SSP(15)
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@ -126,7 +126,7 @@
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* TR0 = FWT(1), FWT(2), FWT(3) .. FWT(14)
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*
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*
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* TR0
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* TR0
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*/
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#ifndef ISO14B_TR0
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# define ISO14B_TR0 ETU_TO_SSP(32)
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@ -140,7 +140,7 @@
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// TR0 max is 151/fsc = 151/848kHz = 302us or 64 samples from FPGA
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// 32 ETU * 9.4395 µS == 302 µS
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// 32 * 8 = 256 sub carrier cycles,
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// 256 / 4 = 64 I/Q pairs.
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// 256 / 4 = 64 I/Q pairs.
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// since 1 I/Q pair after 4 subcarrier cycles at 848kHz subcarrier
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#endif
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@ -195,16 +195,16 @@ static uint32_t iso14b_timeout = FWT_TIMEOUT_14B;
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* Elementary Time Unit (ETU)
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* --------------------------
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* ETU is used to denotate 1 bit period i.e. how long one bit transfer takes.
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*
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*
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* - 128 Carrier cycles / 13.56MHz = 8 Subcarrier units / 848kHz = 1/106kHz = 9.4395 µS
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* - 16 Carrier cycles = 1 Subcarrier unit = 1.17 µS
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*
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* Definition
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* ----------
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* 1 ETU = 128 / ( D x fc )
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* 1 ETU = 128 / ( D x fc )
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* where
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* D = divisor. Which inital is 1
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* fc = carrier frequency
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* fc = carrier frequency
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* gives
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* 1 ETU = 128 / fc
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* 1 ETU = 128 / 13 560 000 = 9.4395 µS
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@ -212,7 +212,7 @@ static uint32_t iso14b_timeout = FWT_TIMEOUT_14B;
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*
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* (note: It seems we are using the subcarrier as base for our time calculations rather than the field clock)
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*
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* - 1 ETU = 1/106 KHz
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* - 1 ETU = 1/106 KHz
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* - 1 ETU = 8 subcarrier units ( 8 / 848kHz )
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* - 1 ETU = 1 bit period
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*
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@ -260,14 +260,14 @@ static uint32_t iso14b_timeout = FWT_TIMEOUT_14B;
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* let calc how long it takes the reader to send a message
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* SOF 10 ETU + 4 data bytes + 2 crc bytes + EOF 2 ETU
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* 10 + (4+2 * 10) + 2 = 72 ETU
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* 72 * 9.4395 = 680 µS or 0.68 ms
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*
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* 72 * 9.4395 = 680 µS or 0.68 ms
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*
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*
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* -> TO VERIFY THIS BELOW <-
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* --------------------------
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* The mode FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_BPSK which we use to simulate tag
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* works like this:
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* Simulation per definition is "inversed" effect on the reader antenna.
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* works like this:
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* Simulation per definition is "inversed" effect on the reader antenna.
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* - A 1-bit input to the FPGA becomes 8 pulses at 847.5kHz (1.18µS / pulse) == 9.44us
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* - A 0-bit input to the FPGA becomes an unmodulated time of 1.18µS or does it become 8 nonpulses for 9.44us
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*
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@ -278,13 +278,13 @@ static uint32_t iso14b_timeout = FWT_TIMEOUT_14B;
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*
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* FPGA doesn't seem to work with ETU. It seems to work with pulse / duration instead.
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*
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* This means that we are using a bit rate of 106 kbit/s, or fc/128.
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* This means that we are using a bit rate of 106 kbit/s, or fc/128.
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* Oversample by 4, which ought to make things practical for the ARM
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* (fc/32, 423.8 kbits/s, ~52 kbytes/s)
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*
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* We are sampling the signal at FC/32, we are reporting over SSP to PM3 each
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*
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* Current I/Q pair sampling
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* We are sampling the signal at FC/32, we are reporting over SSP to PM3 each
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*
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* Current I/Q pair sampling
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* -------------------------
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* Let us report a correlation every 64 samples. I.e.
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* 1 I/Q pair after 4 subcarrier cycles for the 848kHz subcarrier,
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@ -303,7 +303,7 @@ static uint32_t iso14b_timeout = FWT_TIMEOUT_14B;
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*
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* sample: 3sec == 3000ms
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*
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* 13560000 * 1000 / 128 * 3000 == 13560000000 / 384000 ==
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* 13560000 * 1000 / 128 * 3000 == 13560000000 / 384000 ==
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* 13560000 / 384 = 35312 FWT
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*
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* 35312 * 9.4395 ==
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@ -428,7 +428,7 @@ static void Uart14bInit(uint8_t *data) {
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Uart14bReset();
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}
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// param timeout accepts ETU
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// param timeout accepts ETU
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static void iso14b_set_timeout(uint32_t timeout_etu) {
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uint32_t ssp = ETU_TO_SSP(timeout_etu);
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@ -445,7 +445,7 @@ static void iso14b_set_timeout(uint32_t timeout_etu) {
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// keep track of FWT, also updates the timeout
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static void iso14b_set_fwt(uint8_t fwt) {
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iso14b_fwt = fwt;
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iso14b_set_timeout( 32 << fwt );
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iso14b_set_timeout(32 << fwt);
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}
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static void iso14b_set_maxframesize(uint16_t size) {
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@ -1370,7 +1370,7 @@ static int Get14443bAnswerFromTag(uint8_t *response, uint16_t max_len, uint32_t
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break;
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}
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if (((GetCountSspClkDelta(dma_start_time) ) > timeout) && Demod.state < DEMOD_PHASE_REF_TRAINING) {
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if (((GetCountSspClkDelta(dma_start_time)) > timeout) && Demod.state < DEMOD_PHASE_REF_TRAINING) {
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ret = -1;
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break;
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}
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@ -1402,7 +1402,7 @@ static void TransmitFor14443b_AsReader(uint32_t *start_time) {
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER | FPGA_HF_READER_MODE_SEND_SHALLOW_MOD);
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// TR2 minimum 14 ETUs
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if (*start_time < ISO14B_TR0) {
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// *start_time = DELAY_ARM_TO_TAG;
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@ -1562,15 +1562,15 @@ int iso14443b_apdu(uint8_t const *msg, size_t msg_len, bool send_chaining, void
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uint32_t save_iso14b_timeout_spp = iso14b_timeout;
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// 2 high bits mandatory set to 0b
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// byte1 - WTXM [1..59].
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// 2 high bits mandatory set to 0b
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// byte1 - WTXM [1..59].
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uint8_t wtxm = data_bytes[1] & 0x3F;
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// command FWT = FWT * WTXM
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uint32_t fwt_temp = iso14b_fwt * wtxm;
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// temporarily increase timeout
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iso14b_set_timeout( (32 << fwt_temp));
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iso14b_set_timeout((32 << fwt_temp));
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// Transmit WTX back
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data_bytes[1] = wtxm;
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@ -2176,7 +2176,7 @@ void SendRawCommand14443B_Ex(iso14b_raw_cmd_t *o) {
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// receive buffer
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uint8_t buf[PM3_CMD_DATA_SIZE];
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memset(buf, 0 , sizeof(buf));
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memset(buf, 0, sizeof(buf));
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if (DBGLEVEL > DBG_DEBUG) {
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Dbprintf("14b raw: param, %04x", o->flags);
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}
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@ -2114,50 +2114,50 @@ void SetTag15693Uid(uint8_t *uid) {
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static void init_password_15693_slixl(uint8_t *buffer, uint8_t *pwd, uint8_t *rnd) {
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memcpy(buffer, pwd, 4);
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if(rnd) {
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buffer[0] ^= rnd[0];
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buffer[1] ^= rnd[1];
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buffer[2] ^= rnd[0];
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buffer[3] ^= rnd[1];
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}
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if (rnd) {
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buffer[0] ^= rnd[0];
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buffer[1] ^= rnd[1];
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buffer[2] ^= rnd[0];
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buffer[3] ^= rnd[1];
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}
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}
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static bool get_rnd_15693_slixl(uint32_t start_time, uint32_t *eof_time, uint8_t *rnd) {
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// 0x04, == NXP from manufacture id list.
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uint8_t c[] = {ISO15_REQ_DATARATE_HIGH, ISO15693_GET_RANDOM_NUMBER, 0x04, 0x00, 0x00 };
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AddCrc15(c, 3);
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uint8_t c[] = {ISO15_REQ_DATARATE_HIGH, ISO15693_GET_RANDOM_NUMBER, 0x04, 0x00, 0x00 };
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AddCrc15(c, 3);
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uint8_t recvbuf[ISO15693_MAX_RESPONSE_LENGTH];
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int recvlen = SendDataTag(c, sizeof(c), false, true, recvbuf, sizeof(recvbuf), start_time, ISO15693_READER_TIMEOUT_WRITE, eof_time);
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if (recvlen != 5) {
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return false;
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}
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uint8_t recvbuf[ISO15693_MAX_RESPONSE_LENGTH];
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int recvlen = SendDataTag(c, sizeof(c), false, true, recvbuf, sizeof(recvbuf), start_time, ISO15693_READER_TIMEOUT_WRITE, eof_time);
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if (recvlen != 5) {
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return false;
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}
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if(rnd) {
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memcpy(rnd, &recvbuf[1], 2);
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}
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return true;
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if (rnd) {
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memcpy(rnd, &recvbuf[1], 2);
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}
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return true;
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}
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static uint32_t set_pass_15693_slixl(uint32_t start_time, uint32_t *eof_time, uint8_t pass_id, uint8_t *password) {
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uint8_t rnd[2];
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if (get_rnd_15693_slixl(start_time, eof_time, rnd) == false) {
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return PM3_ETIMEOUT;
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}
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uint8_t rnd[2];
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if (get_rnd_15693_slixl(start_time, eof_time, rnd) == false) {
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return PM3_ETIMEOUT;
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}
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// 0x04, == NXP from manufacture id list.
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uint8_t c[] = {ISO15_REQ_DATARATE_HIGH, ISO15693_SET_PASSWORD, 0x04, pass_id, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
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init_password_15693_slixl(&c[4], password, rnd);
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AddCrc15(c, 8);
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uint8_t c[] = {ISO15_REQ_DATARATE_HIGH, ISO15693_SET_PASSWORD, 0x04, pass_id, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
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init_password_15693_slixl(&c[4], password, rnd);
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AddCrc15(c, 8);
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start_time = *eof_time + DELAY_ISO15693_VICC_TO_VCD_READER;
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uint8_t recvbuf[ISO15693_MAX_RESPONSE_LENGTH];
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int recvlen = SendDataTag(c, sizeof(c), false, true, recvbuf, sizeof(recvbuf), start_time, ISO15693_READER_TIMEOUT_WRITE, eof_time);
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if (recvlen != 3) {
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return PM3_EWRONGANSWER;
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}
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start_time = *eof_time + DELAY_ISO15693_VICC_TO_VCD_READER;
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uint8_t recvbuf[ISO15693_MAX_RESPONSE_LENGTH];
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int recvlen = SendDataTag(c, sizeof(c), false, true, recvbuf, sizeof(recvbuf), start_time, ISO15693_READER_TIMEOUT_WRITE, eof_time);
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if (recvlen != 3) {
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return PM3_EWRONGANSWER;
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}
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return PM3_SUCCESS;
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return PM3_SUCCESS;
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}
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/*
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@ -2226,11 +2226,11 @@ static uint32_t destroy_15693_slixl(uint32_t start_time, uint32_t *eof_time, uin
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*/
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void DisablePrivacySlixLIso15693(uint8_t *password) {
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LED_D_ON();
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Iso15693InitReader();
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StartCountSspClk();
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uint32_t start_time = 0, eof_time = 0;
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// 4 == pass id.
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LED_D_ON();
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Iso15693InitReader();
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StartCountSspClk();
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uint32_t start_time = 0, eof_time = 0;
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// 4 == pass id.
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int res = set_pass_15693_slixl(start_time, &eof_time, 0x10, password);
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reply_ng(CMD_HF_ISO15693_SLIX_L_DISABLE_PRIVACY, res, NULL, 0);
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switch_off();
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@ -878,7 +878,7 @@ void Mifare1ksim(uint16_t flags, uint8_t exitAfterNReads, uint8_t *datain, uint1
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if (blockNo == 4) {
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p_em += blockNo * 16;
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// TLV in NDEF, flip length between
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// TLV in NDEF, flip length between
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// 4 | 03 21 D1 02 1C 53 70 91 01 09 54 02 65 6E 4C 69
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// 0xFF means long length
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||||
// 0xFE mean max short length
|
||||
|
|
|
|||
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Reference in a new issue