github/RRG-Proxmark3
1
0
Fork 0
mirror of https://github.com/RfidResearchGroup/proxmark3.git synced 2025-08-20 13:23:51 -07:00
Code Issues Projects Releases Packages Wiki Activity Actions 4

style of .v files

Browse source
This commit is contained in:
Philippe Teuwen 2019-07-30 22:47:23 +02:00
commit cb439ef58b
24 changed files with 1257 additions and 1257 deletions
Download patch file Download diff file Expand all files Collapse all files

38
fpga/lo_simulate.v
View file

@ -13,7 +13,7 @@ module lo_simulate(
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg,
divisor
divisor
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
@ -23,7 +23,7 @@ module lo_simulate(
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
input [7:0] divisor;
input [7:0] divisor;
// No logic, straight through.
assign pwr_oe3 = 1'b0;
@ -41,15 +41,15 @@ reg clk_state;
always @(posedge pck0)
begin
if(pck_divider == divisor[7:0])
begin
pck_divider <= 8'd0;
clk_state = !clk_state;
end
else
begin
pck_divider <= pck_divider + 1;
end
if(pck_divider == divisor[7:0])
begin
pck_divider <= 8'd0;
clk_state = !clk_state;
end
else
begin
pck_divider <= pck_divider + 1;
end
end
assign adc_clk = ~clk_state;
@ -63,18 +63,18 @@ reg output_state;
always @(posedge pck0)
begin
if((pck_divider == 8'd7) && !clk_state) begin
is_high = (adc_d >= 8'd191);
is_low = (adc_d <= 8'd64);
end
if((pck_divider == 8'd7) && !clk_state) begin
is_high = (adc_d >= 8'd191);
is_low = (adc_d <= 8'd64);
end
end
always @(posedge is_high or posedge is_low)
begin
if(is_high)
output_state <= 1'd1;
else if(is_low)
output_state <= 1'd0;
if(is_high)
output_state <= 1'd1;
else if(is_low)
output_state <= 1'd0;
end
assign ssp_frame = output_state;