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style of .v files

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Philippe Teuwen 2019-07-30 22:47:23 +02:00
commit cb439ef58b
24 changed files with 1257 additions and 1257 deletions
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4
fpga/hi_read_tx.v
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@ -27,7 +27,7 @@ module hi_read_tx(
// low frequency outputs, not relevant
assign pwr_lo = 1'b0;
assign pwr_oe2 = 1'b0;
// The high-frequency stuff. For now, for testing, just bring out the carrier,
// and allow the ARM to modulate it over the SSP.
reg pwr_hi;
@ -75,4 +75,4 @@ assign ssp_din = 1'b0;
assign dbg = ssp_frame;
endmodule
endmodule