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style of .v files
This commit is contained in:
Philippe Teuwen
parent
4c9b95c216
commit
cb439ef58b
24 changed files with 1257 additions and 1257 deletions
160
fpga/hi_flite.v
160
fpga/hi_flite.v
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@ -1,9 +1,9 @@
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//this code demodulates and modulates signal as described in ISO/IEC 18092. That includes packets used for Felica, NFC Tag 3, etc. (which do overlap)
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//simple envelope following algorithm is used (modification of fail0verflow LF one) is used to combat some nasty aliasing effect with testing phone (envelope looked like sine wave)
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//simple envelope following algorithm is used (modification of fail0verflow LF one) is used to combat some nasty aliasing effect with testing phone (envelope looked like sine wave)
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// only 212 kbps (fc/64) for now 414 is relatively straightforward... though for reader, the selection has to come from ARM
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// modulation waits for
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//market sprocket -doesn't really mean anything ;)
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// modulation waits for
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//market sprocket -doesn't really mean anything ;)
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//redefining mod_type: bits 210: bit 2 - reader drive/power on/off, bit 1 - speed bit, 0:212, 1 -424 bit 0: listen or modulate
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@ -15,7 +15,7 @@ module hi_flite(
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cross_hi, cross_lo,
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dbg,
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mod_type // used
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);
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input pck0, ck_1356meg, ck_1356megb;
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output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
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@ -33,7 +33,7 @@ wire speed= mod_type[1];
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wire disabl= mod_type[0];
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// Most off, oe4 for modulation;
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// Trying reader emulation (would presumably just require switching power on, but I am not sure)
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// Trying reader emulation (would presumably just require switching power on, but I am not sure)
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//;// 1'b0;
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assign pwr_lo = 1'b0;
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@ -55,7 +55,7 @@ assign adc_clk = ck_1356meg;
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//minimum values and corresponding thresholds
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reg [8:0] curmin=`imin;
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reg [8:0] curminthres=`ithrmin;
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reg [8:0] curminthres=`ithrmin;
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reg [8:0] curmaxthres=`ithrmax;
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reg [8:0] curmax=`imax;
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@ -103,37 +103,37 @@ always @(posedge adc_clk)
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ssp_cnt <= (ssp_cnt + 1);
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//maybe change it so that ARM sends preamble as well.
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//then: ready bits sent to ARM, 8 bits sent from ARM (all ones), then preamble (all zeros, presumably) - which starts modulation
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//then: ready bits sent to ARM, 8 bits sent from ARM (all ones), then preamble (all zeros, presumably) - which starts modulation
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always @(negedge adc_clk)
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begin
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//count fc/64 - transfer bits to ARM at the rate they are received
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if( ((~speed) && (ssp_cnt[5:0] == 6'b000000)) || (speed &&(ssp_cnt[4:0] == 5'b00000)))
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begin
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ssp_clk <= 1'b1;
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ssp_clk <= 1'b1;
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// if(mod_type[2])
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// begin
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// ssp_din<=outp[0];//after_hysteresis;
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//outp<={1'b0,outp[7:1]};
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//outp<={1'b0,outp[7:1]};
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// end
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// else
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ssp_din <= curbit;
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ssp_din <= curbit;
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//sample ssp_dout
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end
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if( ( (~speed) && (ssp_cnt[5:0] == 6'b100000)) ||(speed && ssp_cnt[4:0] == 5'b10000))
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ssp_clk <= 1'b0;
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if( ( (~speed) && (ssp_cnt[5:0] == 6'b100000)) ||(speed && ssp_cnt[4:0] == 5'b10000))
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ssp_clk <= 1'b0;
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//create frame pulses. TBH, I still don't know what they do exactly, but they are crucial for ARM->FPGA transfer. If the frame is in the beginning of the byte, transfer slows to a crawl for some reason
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// took me a day to figure THAT out.
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// took me a day to figure THAT out.
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if(( (~speed) && (ssp_cnt[8:0] == 9'd31))||(speed && ssp_cnt[7:0] == 8'd15))
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begin
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ssp_frame <= 1'b1;
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ssp_frame <= 1'b1;
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end
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if(( (~speed) && (ssp_cnt[8:0] == 9'b1011111))||(speed &&ssp_cnt[7:0] == 8'b101111) )
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begin
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ssp_frame <= 1'b0;
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ssp_frame <= 1'b0;
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end
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end
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@ -141,23 +141,23 @@ end
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//send current bit (detected in SNIFF mode or the one being modulated in MOD mode, 0 otherwise)
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reg ssp_din;//= outp[0];
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reg ssp_din;//= outp[0];
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//previous signal value, mostly to detect SYNC
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reg prv =1'b1;
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reg[7:0] mid=8'd128; //for simple error correction in mod/demod detection, use maximum of modded/demodded in given interval. Maybe 1 bit is extra? but better safe than sorry.
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reg[7:0] mid=8'd128; //for simple error correction in mod/demod detection, use maximum of modded/demodded in given interval. Maybe 1 bit is extra? but better safe than sorry.
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// set TAGSIM__MODULATE on ARM if we want to write... (frame would get lost if done mid-frame...)
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// start sending over 1s on ssp->arm when we start sending preamble
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reg counting_desync=1'b0; // are we counting bits since last frame?
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reg sending=1'b0; // are we actively modulating?
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reg [11:0] bit_counts=12'd0;///for timeslots... only support ts=0 for now, at 212 speed -512 fullbits from end of frame. One hopes. might remove those?
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reg counting_desync=1'b0; // are we counting bits since last frame?
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reg sending=1'b0; // are we actively modulating?
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reg [11:0] bit_counts=12'd0;///for timeslots... only support ts=0 for now, at 212 speed -512 fullbits from end of frame. One hopes. might remove those?
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//reg [2:0]old_mod;
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@ -166,19 +166,19 @@ reg [11:0] bit_counts=12'd0;///for timeslots... only support ts=0 for now, at 21
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//begin
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//if (mod_type[2]==1&&old_mod[2]==0)
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// bit_counts=0;
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//old_mod=mod_type;
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//old_mod=mod_type;
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//end
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//we need some way to flush bit_counts triggers on mod_type changes don't compile
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reg dlay;
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always @(negedge adc_clk) //every data ping?
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always @(negedge adc_clk) //every data ping?
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begin
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//envelope follow code...
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////////////
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//envelope follow code...
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////////////
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//move the counter to the outside...
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// if (adc_d>=curminthres||try_sync)
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// if (adc_d>=curminthres||try_sync)
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if(fccount==bitmlen)
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begin
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begin
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if((~try_sync)&&(adc_d<curminthres)&&disabl )
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begin
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fccount<=1;
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@ -186,12 +186,12 @@ begin
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else
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begin
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fccount<=0;
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end
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end
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// if (counting_desync)
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// begin
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dlay<=ssp_dout;
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if(bit_counts>768) // should be over ts0 now, without ARM interference... stop counting...
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begin
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begin
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bit_counts<=0;
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// counting_desync<=0;
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end
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@ -199,11 +199,11 @@ begin
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if((power))
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bit_counts<=0;
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else
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bit_counts<=bit_counts+1;
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// end
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bit_counts<=bit_counts+1;
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// end
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end
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else
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begin
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begin
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if((~try_sync)&&(adc_d<curminthres) &&disabl)
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begin
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fccount<=1;
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@ -211,9 +211,9 @@ begin
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else
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begin
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fccount<=fccount+1;
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end
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end
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end
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if (adc_d>curmaxthres) //rising edge
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begin
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case (state)
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@ -230,38 +230,38 @@ begin
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2: begin
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if (adc_d>curmax)
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curmax <= adc_d;
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end
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end
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default:
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begin
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end
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end
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endcase
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after_hysteresis <=1'b1;
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if(try_sync)
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tsinceedge<=0;
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end
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else if (adc_d<curminthres) //falling edge
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begin
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begin
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case (state)
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0: begin
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curmin <=adc_d<`imin? adc_d :`imin;
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curmin <=adc_d<`imin? adc_d :`imin;
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state <=1;
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end
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1: begin
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if (adc_d<curmin)
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curmin <= adc_d;
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curmin <= adc_d;
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end
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2: begin
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curminthres <= ( (curmin>>1)+(curmin>>2)+(curmin>>4)+(curmax>>3)+(curmax>>4));
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curmaxthres <= ( (curmax>>1)+(curmax>>2)+(curmax>>4)+(curmin>>3)+(curmin>>4));
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curmin <=adc_d<`imin? adc_d :`imin;
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state <=1;
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end
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state <=1;
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end
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default:
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begin
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end
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endcase
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end
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endcase
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after_hysteresis <=0;
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if (~try_sync ) //begin modulation, lower edge...
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if (~try_sync ) //begin modulation, lower edge...
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begin
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try_sync <=1;
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//counting_desync<=1'b0;
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@ -271,7 +271,7 @@ begin
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mid <=8'd127;
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tsinceedge<=0;
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prv <=1;
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end
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end
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else
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begin
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tsinceedge<=0;
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@ -282,12 +282,12 @@ begin
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curminthres <= ( (curmin>>1)+(curmin>>2)+(curmin>>4)+(curmax>>3)+(curmax>>4));
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curmaxthres <= ( (curmax>>1)+(curmax>>2)+(curmax>>4)+(curmin>>3)+(curmin>>4));
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state <=0;
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if (try_sync )
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begin
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if (tsinceedge>=(128))
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begin
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//we might need to start counting... assuming ARM wants to reply to the frame.
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//we might need to start counting... assuming ARM wants to reply to the frame.
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// counting_desync<=1'b1;
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bit_counts<=1;// i think? 128 is about 2 bits passed... but 1 also works
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try_sync<=0;
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@ -295,7 +295,7 @@ begin
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curmin <=`imin; //reset envelope
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curmax <=`imax;
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curminthres <=`ithrmin;
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curmaxthres <=`ithrmax;
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curmaxthres <=`ithrmax;
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prv <=1;
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tsinceedge <=0;
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after_hysteresis <=1'b1;
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@ -305,33 +305,33 @@ begin
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else
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tsinceedge<=(tsinceedge+1);
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end
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end
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end
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if (try_sync && tsinceedge<128)
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begin
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//detect bits in their middle ssp sampling is in sync, so it would sample all bits in order
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if (fccount==bithalf)
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begin
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if ((~did_sync) && ((prv==1&&(mid>128))||(prv==0&&(mid<=128))))
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begin
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begin
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//sync the Zero, and set curbit roperly
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did_sync <=1'b1;
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zero <= ~prv;// 1-prv
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curbit <=1;
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end
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else
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end
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else
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curbit <= (mid>128) ? (~zero):zero;
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prv <=(mid>128) ?1:0;
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if(adc_d>curmaxthres)
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prv <=(mid>128) ?1:0;
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if(adc_d>curmaxthres)
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mid <=8'd129;
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else if (adc_d<curminthres)
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else if (adc_d<curminthres)
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mid <=8'd127;
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else
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else
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begin
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if (after_hysteresis)
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begin
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@ -342,24 +342,24 @@ begin
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mid<=8'd127;
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end
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end
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end
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else
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begin
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else
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begin
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if (fccount==bitmlen)
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begin
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// fccount <=0;
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prv <=(mid>128)?1:0;
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prv <=(mid>128)?1:0;
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mid <=128;
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end
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else
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begin
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// minimum-maximum calc
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if(adc_d>curmaxthres)
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if(adc_d>curmaxthres)
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mid <=mid+1;
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else if (adc_d<curminthres)
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else if (adc_d<curminthres)
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mid <=mid-1;
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else
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else
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begin
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if (after_hysteresis)
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begin
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@ -369,14 +369,14 @@ begin
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begin
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mid<=mid-1;
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end
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end
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end
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end
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end
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end
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end
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end
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else
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begin
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end
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sending <=0;
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end
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sending <=0;
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end
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//put modulation here to maintain the correct clock. Seems that some readers are sensitive to that
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reg pwr_hi;
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@ -398,7 +398,7 @@ if (power)
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pwr_oe4 <= mod;//1'b0;
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end
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else
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begin
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begin
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pwr_hi <= 1'b0;
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pwr_oe1 <= 1'b0;
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pwr_oe2 <= 1'b0;
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