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d18c7db 2023-05-30 19:47:27 +02:00
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fpga/xc3s100e-4-vq100.ucf Normal file
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# See the schematic for the pin assignment.
NET "adc_d<0>" LOC = "P79" ;
NET "adc_d<1>" LOC = "P78" ;
NET "adc_d<2>" LOC = "P71" ;
NET "adc_d<3>" LOC = "P70" ;
NET "adc_d<4>" LOC = "P69" ;
NET "adc_d<5>" LOC = "P68" ;
NET "adc_d<6>" LOC = "P67" ;
NET "adc_d<7>" LOC = "P66" ;
#NET "cross_hi" LOC = "P88" ;
#NET "miso" LOC = "P40" ;
NET "adc_clk" LOC = "P65" ;
NET "adc_noe" LOC = "P62" ;
NET "ck_1356meg" LOC = "P88" ;
NET "ck_1356megb" LOC = "P89" ;
NET "cross_lo" LOC = "P90" ;
NET "dbg" LOC = "P22" ;
NET "mosi" LOC = "P43" ;
NET "ncs" LOC = "P40" ;
NET "pck0" LOC = "P36" ;
NET "pwr_hi" LOC = "P85" ;
NET "pwr_lo" LOC = "P83" ;
NET "pwr_oe1" LOC = "P84" ;
NET "pwr_oe2" LOC = "P91" ;
NET "pwr_oe3" LOC = "P92" ;
NET "pwr_oe4" LOC = "P86" ;
NET "spck" LOC = "P39" ;
NET "ssp_clk" LOC = "P33" ;
NET "ssp_din" LOC = "P32" ;
NET "ssp_dout" LOC = "P34" ;
NET "ssp_frame" LOC = "P27" ;
NET "FPGA_SWITCH" LOC = "P38" ;
NET "PWR_LO_EN" LOC = "P94" ;
# definition of Clock nets:
NET "ck_1356meg" TNM_NET = "clk_net_1356" ;
NET "ck_1356megb" TNM_NET = "clk_net_1356b";
NET "pck0" TNM_NET = "clk_net_pck0" ;
NET "spck" TNM_NET = "clk_net_spck" ;
NET "FPGA_SWITCH" CLOCK_DEDICATED_ROUTE = FALSE ;
# Timing specs of clock nets:
TIMEGRP "clk_net_1356_all" = "clk_net_1356" "clk_net_1356b" ;
TIMESPEC "TS_1356MHz" = PERIOD "clk_net_1356_all" 74 ns HIGH 37 ns ;
TIMESPEC "TS_24MHz" = PERIOD "clk_net_pck0" 42 ns HIGH 21 ns ;
TIMESPEC "TS_4MHz" = PERIOD "clk_net_spck" 250 ns HIGH 125 ns ;