Unified fpga folders

fpga/tests/Makefile

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+#-----------------------------------------------------------------------------
+# Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
+#
+# This code is licensed to you under the terms of the GNU GPL, version 2 or,
+# at your option, any later version. See the LICENSE.txt file for the text of
+# the license.
+#-----------------------------------------------------------------------------
+MKDIR = mkdir -p
+TEST_OUTDIR = tb_tmp
+
+TB_SOURCES = \
+	tb_lp20khz_1MSa_iir_filter.v \
+	tb_min_max_tracker.v \
+	tb_lf_edge_detect.v
+
+TBS = $(TB_SOURCES:.v=.vvp)
+
+TB_DATA = \
+	pcf7931_write1byte_1MSA_data \
+	pcf7931_read_1MSA_data
+
+all: $(TBS) tests
+
+%.vvp: %.v
+	iverilog -I .. -o $@ $<
+
+clean:
+	rm -rf *.vvp $(TEST_OUTDIR)
+
+tests: tb_lp20khz_1MSa_iir_filter tb_min_max_tracker tb_lf_edge_detect
+
+tb_lp20khz_1MSa_iir_filter: tb_lp20khz_1MSa_iir_filter.vvp | test_dir
+	@printf "Testing $@\n"
+	@for d in $(TB_DATA); do \
+		$(call run_test,$@.vvp,$$d,in); \
+		$(call check_golden,$$d,filtered); \
+	done; \
+	rm -f $(TEST_OUTDIR)/data.*
+
+tb_min_max_tracker: tb_min_max_tracker.vvp | test_dir
+	@printf "Testing $@\n"
+	@for d in $(TB_DATA); do \
+		$(call run_test,$@.vvp,$$d,in filtered.gold); \
+		$(call check_golden,$$d,min); \
+		$(call check_golden,$$d,max); \
+	done; \
+	rm -f $(TEST_OUTDIR)/data.*
+
+tb_lf_edge_detect: tb_lf_edge_detect.vvp | test_dir
+	@printf "Testing $@\n"
+	@for d in $(TB_DATA); do \
+		$(call run_test,$@.vvp,$$d,in filtered.gold); \
+		$(call check_golden,$$d,min); \
+		$(call check_golden,$$d,max); \
+		$(call check_golden,$$d,state); \
+		$(call check_golden,$$d,toggle); \
+		$(call check_golden,$$d,high); \
+		$(call check_golden,$$d,highz); \
+		$(call check_golden,$$d,lowz); \
+		$(call check_golden,$$d,low); \
+	done; \
+	rm -f $(TEST_OUTDIR)/data.*
+
+test_dir:
+	@if [ ! -d $(TEST_OUTDIR) ] ; then $(MKDIR) $(TEST_OUTDIR) ; fi
+
+.PHONY: all clean
+
+# $(1) = basename
+# $(2) = extension to check
+check_golden = \
+	printf "        Checking $(1).$(2)... "; \
+	mv $(TEST_OUTDIR)/data.$(2) $(TEST_OUTDIR)/$(1).$(2); \
+	if cmp -s tb_data/$(1).$(2).gold $(TEST_OUTDIR)/$(1).$(2); then \
+		printf "OK\n"; \
+	else \
+		printf "ERROR\n"; \
+	fi
+
+# $(1) = vvp file
+# $(2) = data basename
+# $(3) = data extensions to copy
+run_test = \
+	env echo "    With $(2)... "; \
+	cp tb_data/$(2).time $(TEST_OUTDIR); \
+	for e in $(3); do cp tb_data/$(2).$$e $(TEST_OUTDIR)/data.$$e; done; \
+	./$(1)

fpga/tests/plot_edgedetect.py

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+#!/usr/bin/env python3
+#-----------------------------------------------------------------------------
+# Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
+#
+# This code is licensed to you under the terms of the GNU GPL, version 2 or,
+# at your option, any later version. See the LICENSE.txt file for the text of
+# the license.
+#-----------------------------------------------------------------------------
+
+import sys
+try:
+    import numpy
+except ModuleNotFoundError:
+    print("Please install numpy module first.")
+    sys.exit(1)
+
+try:
+    import matplotlib.pyplot as plt
+except ModuleNotFoundError:
+    print("Please install matplotlib module first.")
+    sys.exit(1)
+
+if len(sys.argv) != 2:
+    print("Usage: %s <basename>" % sys.argv[0])
+    sys.exit(1)
+
+BASENAME = sys.argv[1]
+
+nx = numpy.fromfile(BASENAME + ".time")
+
+def plot_time(dat1):
+    plt.plot(nx, dat1)
+
+sig = bytearray(open(BASENAME + ".filtered", 'rb').read())
+min_vals = bytearray(open(BASENAME + ".min", 'rb').read())
+max_vals = bytearray(open(BASENAME + ".max", 'rb').read())
+states = bytearray(open(BASENAME + ".state", 'rb').read())
+toggles = bytearray(open(BASENAME+ ".toggle", 'rb').read())
+high = bytearray(open(BASENAME + ".high", 'rb').read())
+highz = bytearray(open(BASENAME + ".highz", 'rb').read())
+lowz = bytearray(open(BASENAME + ".lowz", 'rb').read())
+low = bytearray(open(BASENAME + ".low", 'rb').read())
+
+plot_time(sig)
+plot_time(min_vals)
+plot_time(max_vals)
+plot_time(states)
+plot_time(toggles)
+plot_time(high)
+plot_time(highz)
+plot_time(lowz)
+plot_time(low)
+
+plt.show()

fpga/tests/sim.tcl

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+#------------------------------------------------------------------------------
+# Run the simulation testbench in ModelSim: recompile both Verilog source
+# files, then start the simulation, add a lot of signals to the waveform
+# viewer, and run. I should (TODO) fix the absolute paths at some point.
+#
+# Jonathan Westhues, Mar 2006
+#------------------------------------------------------------------------------
+
+vlog -work work -O0 C:/depot/proximity/mark3/fpga/fpga.v
+vlog -work work -O0 C:/depot/proximity/mark3/fpga/fpga_tb.v
+
+vsim work.fpga_tb
+
+add wave sim:/fpga_tb/adc_clk
+add wave sim:/fpga_tb/adc_d
+add wave sim:/fpga_tb/pwr_lo
+add wave sim:/fpga_tb/ssp_clk
+add wave sim:/fpga_tb/ssp_frame
+add wave sim:/fpga_tb/ssp_din
+add wave sim:/fpga_tb/ssp_dout
+
+add wave sim:/fpga_tb/dut/clk_lo
+add wave sim:/fpga_tb/dut/pck_divider
+add wave sim:/fpga_tb/dut/carrier_divider_lo
+add wave sim:/fpga_tb/dut/conf_word
+
+run 30000

fpga/tests/tb_lf_edge_detect.v

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+//-----------------------------------------------------------------------------
+// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
+//
+// This code is licensed to you under the terms of the GNU GPL, version 2 or,
+// at your option, any later version. See the LICENSE.txt file for the text of
+// the license.
+//-----------------------------------------------------------------------------
+// testbench for lf_edge_detect
+`include "lf_edge_detect.v"
+
+`define FIN "tb_tmp/data.filtered.gold"
+`define FOUT_MIN "tb_tmp/data.min"
+`define FOUT_MAX "tb_tmp/data.max"
+`define FOUT_STATE "tb_tmp/data.state"
+`define FOUT_TOGGLE "tb_tmp/data.toggle"
+`define FOUT_HIGH "tb_tmp/data.high"
+`define FOUT_HIGHZ "tb_tmp/data.highz"
+`define FOUT_LOWZ "tb_tmp/data.lowz"
+`define FOUT_LOW "tb_tmp/data.low"
+
+module lf_edge_detect_tb;
+
+    integer fin, fout_state, fout_toggle;
+    integer fout_high, fout_highz, fout_lowz, fout_low, fout_min, fout_max;
+    integer r;
+
+    reg clk = 0;
+    reg [7:0] adc_d;
+    wire adc_clk;
+    wire data_rdy;
+    wire edge_state;
+    wire edge_toggle;
+
+    wire [7:0] high_threshold;
+    wire [7:0] highz_threshold;
+    wire [7:0] lowz_threshold;
+    wire [7:0] low_threshold;
+    wire [7:0] max;
+    wire [7:0] min;
+
+    initial
+    begin
+        clk = 0;
+        fin = $fopen(`FIN, "r");
+        if (!fin) begin
+            $display("ERROR: can't open the data file");
+            $finish;
+        end
+        fout_min = $fopen(`FOUT_MIN, "w+");
+        fout_max = $fopen(`FOUT_MAX, "w+");
+        fout_state = $fopen(`FOUT_STATE, "w+");
+        fout_toggle = $fopen(`FOUT_TOGGLE, "w+");
+        fout_high = $fopen(`FOUT_HIGH, "w+");
+        fout_highz = $fopen(`FOUT_HIGHZ, "w+");
+        fout_lowz = $fopen(`FOUT_LOWZ, "w+");
+        fout_low = $fopen(`FOUT_LOW, "w+");
+        if (!$feof(fin))
+            adc_d = $fgetc(fin); // read the first value
+    end
+
+    always
+        # 1 clk = !clk;
+
+    // input
+    initial
+    begin
+        while (!$feof(fin)) begin
+            @(negedge clk) adc_d <= $fgetc(fin);
+        end
+
+        if ($feof(fin))
+        begin
+            # 3 $fclose(fin);
+            $fclose(fout_state);
+            $fclose(fout_toggle);
+            $fclose(fout_high);
+            $fclose(fout_highz);
+            $fclose(fout_lowz);
+            $fclose(fout_low);
+            $fclose(fout_min);
+            $fclose(fout_max);
+            $finish;
+        end
+    end
+
+    initial
+    begin
+        // $monitor("%d\t S: %b, E: %b", $time, edge_state, edge_toggle);
+    end
+
+    // output
+    always @(negedge clk)
+    if ($time > 2) begin
+        r = $fputc(min, fout_min);
+        r = $fputc(max, fout_max);
+        r = $fputc(edge_state, fout_state);
+        r = $fputc(edge_toggle, fout_toggle);
+        r = $fputc(high_threshold, fout_high);
+        r = $fputc(highz_threshold, fout_highz);
+        r = $fputc(lowz_threshold, fout_lowz);
+        r = $fputc(low_threshold, fout_low);
+    end
+
+    // module to test
+    lf_edge_detect detect(clk, adc_d, 8'd127,
+        max, min,
+        high_threshold, highz_threshold,
+        lowz_threshold, low_threshold,
+        edge_state, edge_toggle);
+
+endmodule

fpga/tests/tb_lp20khz_1MSa_iir_filter.v

@@ -0,0 +1,55 @@
+//-----------------------------------------------------------------------------
+// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
+//
+// This code is licensed to you under the terms of the GNU GPL, version 2 or,
+// at your option, any later version. See the LICENSE.txt file for the text of
+// the license.
+//-----------------------------------------------------------------------------
+// testbench for lp20khz_1MSa_iir_filter
+`include "lp20khz_1MSa_iir_filter.v"
+
+`define FIN "tb_tmp/data.in"
+`define FOUT "tb_tmp/data.filtered"
+
+module lp20khz_1MSa_iir_filter_tb;
+
+    integer fin, fout, r;
+
+    reg clk;
+    reg [7:0] adc_d;
+    wire data_rdy;
+    wire [7:0] adc_filtered;
+
+    initial
+    begin
+        clk = 0;
+        fin = $fopen(`FIN, "r");
+        if (!fin) begin
+            $display("ERROR: can't open the data file");
+            $finish;
+        end
+        fout = $fopen(`FOUT, "w+");
+        if (!$feof(fin))
+            adc_d = $fgetc(fin); // read the first value
+    end
+
+    always
+        # 1 clk = !clk;
+
+    always @(posedge clk)
+        if (data_rdy) begin
+            if ($time > 1)
+                r = $fputc(adc_filtered, fout);
+            if (!$feof(fin))
+                adc_d <= $fgetc(fin);
+            else begin
+                $fclose(fin);
+                $fclose(fout);
+                $finish;
+            end
+        end
+
+    // module to test
+    lp20khz_1MSa_iir_filter filter(clk, adc_d, data_rdy, adc_filtered);
+
+endmodule

fpga/tests/tb_min_max_tracker.v

@@ -0,0 +1,74 @@
+//-----------------------------------------------------------------------------
+// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
+//
+// This code is licensed to you under the terms of the GNU GPL, version 2 or,
+// at your option, any later version. See the LICENSE.txt file for the text of
+// the license.
+//-----------------------------------------------------------------------------
+// testbench for min_max_tracker
+`include "min_max_tracker.v"
+
+`define FIN "tb_tmp/data.filtered.gold"
+`define FOUT_MIN "tb_tmp/data.min"
+`define FOUT_MAX "tb_tmp/data.max"
+
+module min_max_tracker_tb;
+
+    integer fin;
+    integer fout_min, fout_max;
+    integer r;
+
+    reg clk;
+    reg [7:0] adc_d;
+    wire [7:0] min;
+    wire [7:0] max;
+
+    initial
+    begin
+        clk = 0;
+        fin = $fopen(`FIN, "r");
+        if (!fin) begin
+            $display("ERROR: can't open the data file");
+            $finish;
+        end
+        fout_min = $fopen(`FOUT_MIN, "w+");
+        fout_max = $fopen(`FOUT_MAX, "w+");
+        if (!$feof(fin))
+            adc_d = $fgetc(fin); // read the first value
+    end
+
+    always
+        # 1 clk = !clk;
+
+    // input
+    initial
+    begin
+        while (!$feof(fin)) begin
+            @(negedge clk) adc_d <= $fgetc(fin);
+        end
+
+        if ($feof(fin))
+        begin
+            # 3 $fclose(fin);
+            $fclose(fout_min);
+            $fclose(fout_max);
+            $finish;
+        end
+    end
+
+    initial
+    begin
+        // $monitor("%d\t min: %x, max: %x", $time, min, max);
+    end
+
+    // output
+    always @(negedge clk)
+    if ($time > 2) begin
+        r = $fputc(min, fout_min);
+        r = $fputc(max, fout_max);
+    end
+
+    // module to test
+    min_max_tracker tracker(clk, adc_d, 8'd127, min, max);
+
+endmodule

fpga/tests/testbed_fpga.v

@@ -0,0 +1,66 @@
+//-----------------------------------------------------------------------------
+// Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// See LICENSE.txt for the text of the license.
+//-----------------------------------------------------------------------------
+
+`include "fpga.v"
+
+module testbed_fpga;
+    reg spck, mosi, ncs;
+    wire miso;
+    reg pck0i, ck_1356meg, ck_1356megb;
+    wire pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
+    reg [7:0] adc_d;
+    wire adc_clk, adc_noe;
+    reg ssp_dout;
+    wire ssp_frame, ssp_din, ssp_clk;
+
+    fpga dut(
+        spck, miso, mosi, ncs,
+        pck0i, ck_1356meg, ck_1356megb,
+        pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
+        adc_d, adc_clk, adc_noe,
+        ssp_frame, ssp_din, ssp_dout, ssp_clk
+    );
+
+    integer i;
+
+    initial begin
+
+        // init inputs
+        #5 ncs=1;
+        #5 spck = 1;
+        #5 mosi = 1;
+
+        #50 ncs=0;
+        for (i = 0 ;  i < 8 ;  i = i + 1) begin
+            #5 mosi = $random;
+            #5 spck = 0;
+            #5 spck = 1;
+        end
+        #5 ncs=1;
+
+        #50 ncs=0;
+        for (i = 0 ;  i < 8 ;  i = i + 1) begin
+            #5 mosi = $random;
+            #5 spck = 0;
+            #5 spck = 1;
+        end
+        #5 ncs=1;
+
+        #50 mosi=1;
+        $finish;
+    end
+
+endmodule // main

fpga/tests/testbed_hi_read_tx.v

@@ -0,0 +1,125 @@
+//-----------------------------------------------------------------------------
+// Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// See LICENSE.txt for the text of the license.
+//-----------------------------------------------------------------------------
+
+`include "hi_read_tx.v"
+
+/*
+    pck0            - input main 24MHz clock (PLL / 4)
+    [7:0] adc_d     - input data from A/D converter
+    shallow_modulation  - modulation type
+
+    pwr_lo          - output to coil drivers (ssp_clk / 8)
+    adc_clk         - output A/D clock signal
+    ssp_frame       - output SSS frame indicator (goes high while the 8 bits are shifted)
+    ssp_din         - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
+    ssp_clk         - output SSP clock signal
+
+    ck_1356meg      - input unused
+    ck_1356megb     - input unused
+    ssp_dout        - input unused
+    cross_hi        - input unused
+    cross_lo        - input unused
+
+    pwr_hi          - output unused, tied low
+    pwr_oe1         - output unused, undefined
+    pwr_oe2         - output unused, undefined
+    pwr_oe3         - output unused, undefined
+    pwr_oe4         - output unused, undefined
+    dbg             - output alias for adc_clk
+*/
+
+module testbed_hi_read_tx;
+    reg  pck0;
+    reg  [7:0] adc_d;
+    reg  shallow_modulation;
+
+    wire pwr_lo;
+    wire adc_clk;
+    reg ck_1356meg;
+    reg  ck_1356megb;
+    wire ssp_frame;
+    wire ssp_din;
+    wire ssp_clk;
+    reg  ssp_dout;
+    wire pwr_hi;
+    wire pwr_oe1;
+    wire pwr_oe2;
+    wire pwr_oe3;
+    wire pwr_oe4;
+    wire cross_lo;
+    wire cross_hi;
+    wire dbg;
+
+    hi_read_tx #(5,200) dut(
+    .pck0(pck0),
+    .ck_1356meg(ck_1356meg),
+    .ck_1356megb(ck_1356megb),
+    .pwr_lo(pwr_lo),
+    .pwr_hi(pwr_hi),
+    .pwr_oe1(pwr_oe1),
+    .pwr_oe2(pwr_oe2),
+    .pwr_oe3(pwr_oe3),
+    .pwr_oe4(pwr_oe4),
+    .adc_d(adc_d),
+    .adc_clk(adc_clk),
+    .ssp_frame(ssp_frame),
+    .ssp_din(ssp_din),
+    .ssp_dout(ssp_dout),
+    .ssp_clk(ssp_clk),
+    .cross_hi(cross_hi),
+    .cross_lo(cross_lo),
+    .dbg(dbg),
+    .shallow_modulation(shallow_modulation)
+    );
+
+    integer idx, i;
+
+    // main clock
+    always #5 begin
+        ck_1356megb = !ck_1356megb;
+        ck_1356meg = ck_1356megb;
+    end
+
+    //crank DUT
+    task crank_dut;
+    begin
+        @(posedge ssp_clk) ;
+        ssp_dout = $random;
+    end
+    endtask
+
+    initial begin
+
+        // init inputs
+        ck_1356megb = 0;
+        adc_d = 0;
+        ssp_dout=0;
+
+        // shallow modulation off
+        shallow_modulation=0;
+        for (i = 0 ;  i < 16 ;  i = i + 1) begin
+            crank_dut;
+        end
+
+        // shallow modulation on
+        shallow_modulation=1;
+        for (i = 0 ;  i < 16 ;  i = i + 1) begin
+            crank_dut;
+        end
+        $finish;
+    end
+
+endmodule // main

fpga/tests/testbed_hi_simulate.v

@@ -0,0 +1,132 @@
+//-----------------------------------------------------------------------------
+// Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// See LICENSE.txt for the text of the license.
+//-----------------------------------------------------------------------------
+
+`include "hi_simulate.v"
+
+/*
+    pck0            - input main 24MHz clock (PLL / 4)
+    [7:0] adc_d     - input data from A/D converter
+    mod_type    - modulation type
+
+    pwr_lo          - output to coil drivers (ssp_clk / 8)
+    adc_clk         - output A/D clock signal
+    ssp_frame       - output SSS frame indicator (goes high while the 8 bits are shifted)
+    ssp_din         - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
+    ssp_clk         - output SSP clock signal
+
+    ck_1356meg      - input unused
+    ck_1356megb     - input unused
+    ssp_dout        - input unused
+    cross_hi        - input unused
+    cross_lo        - input unused
+
+    pwr_hi          - output unused, tied low
+    pwr_oe1         - output unused, undefined
+    pwr_oe2         - output unused, undefined
+    pwr_oe3         - output unused, undefined
+    pwr_oe4         - output unused, undefined
+    dbg             - output alias for adc_clk
+*/
+
+module testbed_hi_simulate;
+    reg  pck0;
+    reg  [7:0] adc_d;
+    reg  mod_type;
+
+    wire pwr_lo;
+    wire adc_clk;
+    reg ck_1356meg;
+    reg  ck_1356megb;
+    wire ssp_frame;
+    wire ssp_din;
+    wire ssp_clk;
+    reg  ssp_dout;
+    wire pwr_hi;
+    wire pwr_oe1;
+    wire pwr_oe2;
+    wire pwr_oe3;
+    wire pwr_oe4;
+    wire cross_lo;
+    wire cross_hi;
+    wire dbg;
+
+    hi_simulate #(5,200) dut(
+    .pck0(pck0),
+    .ck_1356meg(ck_1356meg),
+    .ck_1356megb(ck_1356megb),
+    .pwr_lo(pwr_lo),
+    .pwr_hi(pwr_hi),
+    .pwr_oe1(pwr_oe1),
+    .pwr_oe2(pwr_oe2),
+    .pwr_oe3(pwr_oe3),
+    .pwr_oe4(pwr_oe4),
+    .adc_d(adc_d),
+    .adc_clk(adc_clk),
+    .ssp_frame(ssp_frame),
+    .ssp_din(ssp_din),
+    .ssp_dout(ssp_dout),
+    .ssp_clk(ssp_clk),
+    .cross_hi(cross_hi),
+    .cross_lo(cross_lo),
+    .dbg(dbg),
+    .mod_type(mod_type)
+    );
+
+    integer idx, i;
+
+    // main clock
+    always #5 begin
+        ck_1356megb = !ck_1356megb;
+        ck_1356meg = ck_1356megb;
+    end
+
+    always begin
+        @(negedge adc_clk) ;
+        adc_d = $random;
+    end
+
+    //crank DUT
+    task crank_dut;
+        begin
+            @(negedge ssp_clk) ;
+            ssp_dout = $random;
+        end
+    endtask
+
+    initial begin
+
+        // init inputs
+        ck_1356megb = 0;
+        // random values
+        adc_d = 0;
+        ssp_dout=1;
+
+        // shallow modulation off
+        mod_type=0;
+        for (i = 0 ;  i < 16 ;  i = i + 1) begin
+            crank_dut;
+        end
+
+        // shallow modulation on
+        mod_type=1;
+        for (i = 0 ;  i < 16 ;  i = i + 1) begin
+            crank_dut;
+        end
+        $finish;
+    end
+
+endmodule // main
+

fpga/tests/testbed_lo_read.v

@@ -0,0 +1,117 @@
+//-----------------------------------------------------------------------------
+// Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// See LICENSE.txt for the text of the license.
+//-----------------------------------------------------------------------------
+
+`include "lo_read.v"
+/*
+    pck0            - input main 24MHz clock (PLL / 4)
+    [7:0] adc_d     - input data from A/D converter
+    lo_is_125khz    - input freq selector (1=125kHz, 0=136kHz)
+
+    pwr_lo          - output to coil drivers (ssp_clk / 8)
+    adc_clk         - output A/D clock signal
+    ssp_frame       - output SSS frame indicator (goes high while the 8 bits are shifted)
+    ssp_din         - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
+    ssp_clk         - output SSP clock signal 1MHz/1.09MHz (pck0 / 2*(11+lo_is_125khz) )
+
+    ck_1356meg      - input unused
+    ck_1356megb     - input unused
+    ssp_dout        - input unused
+    cross_hi        - input unused
+    cross_lo        - input unused
+
+    pwr_hi          - output unused, tied low
+    pwr_oe1         - output unused, undefined
+    pwr_oe2         - output unused, undefined
+    pwr_oe3         - output unused, undefined
+    pwr_oe4         - output unused, undefined
+    dbg             - output alias for adc_clk
+*/
+
+module testbed_lo_read;
+    reg  pck0;
+    reg  [7:0] adc_d;
+    reg  lo_is_125khz;
+    reg [15:0] divisor;
+
+    wire pwr_lo;
+    wire adc_clk;
+    wire ck_1356meg;
+    wire ck_1356megb;
+    wire ssp_frame;
+    wire ssp_din;
+    wire ssp_clk;
+    reg ssp_dout;
+    wire pwr_hi;
+    wire pwr_oe1;
+    wire pwr_oe2;
+    wire pwr_oe3;
+    wire pwr_oe4;
+    wire cross_lo;
+    wire cross_hi;
+    wire dbg;
+
+    lo_read #(5,10) dut(
+    .pck0(pck0),
+    .ck_1356meg(ck_1356meg),
+    .ck_1356megb(ck_1356megb),
+    .pwr_lo(pwr_lo),
+    .pwr_hi(pwr_hi),
+    .pwr_oe1(pwr_oe1),
+    .pwr_oe2(pwr_oe2),
+    .pwr_oe3(pwr_oe3),
+    .pwr_oe4(pwr_oe4),
+    .adc_d(adc_d),
+    .adc_clk(adc_clk),
+    .ssp_frame(ssp_frame),
+    .ssp_din(ssp_din),
+    .ssp_dout(ssp_dout),
+    .ssp_clk(ssp_clk),
+    .cross_hi(cross_hi),
+    .cross_lo(cross_lo),
+    .dbg(dbg),
+    .lo_is_125khz(lo_is_125khz),
+    .divisor(divisor)
+    );
+
+    integer idx, i, adc_val=8;
+
+    // main clock
+    always #5 pck0 = !pck0;
+
+    task crank_dut;
+    begin
+        @(posedge adc_clk) ;
+        adc_d = adc_val;
+        adc_val = (adc_val *2) + 53;
+    end
+    endtask
+
+    initial begin
+
+        // init inputs
+        pck0 = 0;
+        adc_d = 0;
+        ssp_dout = 0;
+        lo_is_125khz = 1;
+        divisor = 255;  //min 16, 95=125kHz, max 255
+
+        // simulate 4 A/D cycles at 125kHz
+        for (i = 0 ;  i < 8 ;  i = i + 1) begin
+            crank_dut;
+        end
+        $finish;
+    end
+endmodule // main

fpga/tests/testbed_lo_simulate.v

@@ -0,0 +1,117 @@
+//-----------------------------------------------------------------------------
+// Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// See LICENSE.txt for the text of the license.
+//-----------------------------------------------------------------------------
+
+`include "lo_simulate.v"
+
+/*
+    pck0            - input main 24MHz clock (PLL / 4)
+    [7:0] adc_d     - input data from A/D converter
+
+
+    pwr_lo          - output to coil drivers (ssp_clk / 8)
+    adc_clk         - output A/D clock signal
+    ssp_frame       - output SSS frame indicator (goes high while the 8 bits are shifted)
+    ssp_din         - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
+    ssp_clk         - output SSP clock signal
+
+    ck_1356meg      - input unused
+    ck_1356megb     - input unused
+    ssp_dout        - input unused
+    cross_hi        - input unused
+    cross_lo        - input unused
+
+    pwr_hi          - output unused, tied low
+    pwr_oe1         - output unused, undefined
+    pwr_oe2         - output unused, undefined
+    pwr_oe3         - output unused, undefined
+    pwr_oe4         - output unused, undefined
+    dbg             - output alias for adc_clk
+*/
+
+module testbed_lo_simulate;
+    reg  pck0;
+    reg  [7:0] adc_d;
+
+
+    wire pwr_lo;
+    wire adc_clk;
+    wire ck_1356meg;
+    wire ck_1356megb;
+    wire ssp_frame;
+    wire ssp_din;
+    wire ssp_clk;
+    reg  ssp_dout;
+    wire pwr_hi;
+    wire pwr_oe1;
+    wire pwr_oe2;
+    wire pwr_oe3;
+    wire pwr_oe4;
+    reg  cross_lo;
+    wire cross_hi;
+    wire dbg;
+
+    lo_simulate #(5,200) dut(
+    .pck0(pck0),
+    .ck_1356meg(ck_1356meg),
+    .ck_1356megb(ck_1356megb),
+    .pwr_lo(pwr_lo),
+    .pwr_hi(pwr_hi),
+    .pwr_oe1(pwr_oe1),
+    .pwr_oe2(pwr_oe2),
+    .pwr_oe3(pwr_oe3),
+    .pwr_oe4(pwr_oe4),
+    .adc_d(adc_d),
+    .adc_clk(adc_clk),
+    .ssp_frame(ssp_frame),
+    .ssp_din(ssp_din),
+    .ssp_dout(ssp_dout),
+    .ssp_clk(ssp_clk),
+    .cross_hi(cross_hi),
+    .cross_lo(cross_lo),
+    .dbg(dbg)
+    );
+
+
+    integer i, counter=0;
+
+    // main clock
+    always #5 pck0 = !pck0;
+
+    //cross_lo is not really synced to pck0 but it's roughly pck0/192 (24MHz/192=125kHz)
+    task crank_dut;
+    begin
+        @(posedge pck0) ;
+        counter = counter + 1;
+        if (counter == 192) begin
+            counter = 0;
+            ssp_dout = $random;
+            cross_lo = 1;
+        end else begin
+            cross_lo = 0;
+        end
+
+    end
+    endtask
+
+    initial begin
+        pck0 = 0;
+        for (i = 0 ;  i < 4096 ;  i = i + 1) begin
+            crank_dut;
+        end
+        $finish;
+    end
+
+endmodule // main