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LF HITAG: Adjust timing for LF ADC measurements to increase stability when the tag is in public mode/TTF mode

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Signed-off-by: rfidgeek1337 <rfidgeek1337@proton.me>
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rfidgeek1337 2025-06-11 18:07:51 +02:00 • committed by GitHub
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1 changed files with 7 additions and 2 deletions
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9
armsrc/lfadc.c
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@ -236,8 +236,13 @@ void lf_init(bool reader, bool simulate, bool ledcontrol) {
FpgaSetupSsc(FPGA_MAJOR_MODE_LF_READER); FpgaSetupSsc(FPGA_MAJOR_MODE_LF_READER);
// When in reader mode, give the field a bit of time to settle. // When in reader mode, give the field a bit of time to settle.
// 313T0 = 313 * 8us = 2504us = 2.5ms Hitag2 tags needs to be fully powered. // Optimal timing window for LF ADC measurements to be performed:
SpinDelay(10); // minimum: 313T0 = 313 * 8us = 2504us = 2.50ms - Hitag2 tag internal powerup time
// 280T0 = 280 * 8us = 2240us = 2.24ms - HitagS minimum time before the first command (powerup time)
// maximum: 545T0 = 545 * 8us = 4360us = 4.36ms - Hitag2 command waiting time before it starts transmitting in public mode (if configured so)
// 565T0 = 565 * 8us = 4520us = 4.52ms - HitagS waiting time before entering TTF mode
// Thus (2.50 ms + 4.36 ms) / 2 ~= 3 ms, should be a good timing for both tag models
SpinDelay(3);
// Steal this pin from the SSP (SPI communication channel with fpga) and use it to control the modulation // Steal this pin from the SSP (SPI communication channel with fpga) and use it to control the modulation
AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT; AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;