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https://github.com/RfidResearchGroup/proxmark3.git
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Merged hi_reader and hi_reader_15 into one file
hi_reader_15 was a superset of hi_reader, now uses conditional compile from Makefile like the other files to select compilations options
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Alex
parent
279d6486c1
commit
c41c685807
4 changed files with 139 additions and 499 deletions
170
fpga/hi_reader.v
170
fpga/hi_reader.v
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@ -13,7 +13,7 @@
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//
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// See LICENSE.txt for the text of the license.
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//-----------------------------------------------------------------------------
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//`include "define.v"
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// with optional support for iso15 2sc mode slected with compiler define WITH_HF_15
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module hi_reader(
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input ck_1356meg,
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@ -63,7 +63,6 @@ begin
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end
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end
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// Let us report a correlation every 64 samples. I.e.
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// one Q/I pair after 4 subcarrier cycles for the 848kHz subcarrier,
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// one Q/I pair after 2 subcarrier cycles for the 424kHz subcarriers,
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@ -71,10 +70,105 @@ end
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// We need a 6-bit counter for the timing.
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reg [5:0] corr_i_cnt;
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always @(negedge adc_clk)
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begin
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corr_i_cnt <= corr_i_cnt + 1;
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end
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`ifdef WITH_HF_15
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reg [1:0] fskout = 2'd0;
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reg last0 = 1'b0;
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reg [7:0] avg = 8'd0;
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reg [127:0] avg128 = 128'd0;
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reg [7:0] diff16 = 8'd0;
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reg [7:0] diff28 = 8'd0;
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reg [7:0] diff32 = 8'd0;
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reg [11:0] match16 = 12'd0;
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reg [11:0] match32 = 12'd0;
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reg [11:0] match28 = 12'd0;
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always @(negedge adc_clk)
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begin
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if (corr_i_cnt[0] == 1'b0) // every 2 clock
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avg = adc_d[7:1];
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else
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begin
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avg = avg + adc_d[7:1];
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if (corr_i_cnt[0] == 1'b1) // every 2 clock
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begin
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if (avg > avg128[63:56])
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diff16 = avg - avg128[63:56];
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else
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diff16 = avg128[63:56] - avg;
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if (avg > avg128[111:104])
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diff28 = avg - avg128[111:104];
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else
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diff28 = avg128[111:104] - avg;
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if (avg > avg128[127:120])
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diff32 = avg - avg128[127:120];
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else
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diff32 = avg128[127:120] - avg;
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avg128[127:8] = avg128[119:0];
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avg128[7:0] = avg;
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if (corr_i_cnt[4:1] == 4'b0000) // every 32 clock (8*4)
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begin
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match16 = diff16;
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match28 = diff28;
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match32 = diff32;
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end
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else
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begin
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match16 = match16 + diff16;
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match28 = match28 + diff28;
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match32 = match32 + diff32;
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if (corr_i_cnt[4:1] == 4'b1111) // every 32 clock (8*4)
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begin
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last0 = (fskout == 2'b0);
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if (match16 < 12'd64 && last0)
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fskout = 2'b00; // not yet started
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else if ((match16 | match28 | match32) == 12'b0)
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fskout = 2'b00; // signal likely ended
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else if (((match16 <= match28 + 12'd16) && (match16 <= match32+ 12'd16)) ||
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(match28 <= 12'd16 && match32 <= 12'd16))
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begin
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if (!last0)
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fskout = 2'b11; // 16 match better than 28 or 32 but already started
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end
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else
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begin
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if (match28 < match32)
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begin
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diff28 = match32 - match28;
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diff16 = match16 - match28;
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if (diff28*2 > diff16)
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fskout = 2'b01;
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else if (!last0)
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begin
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fskout = 2'b01;
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end
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end
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else //if (match32 <= match28)
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begin
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diff32 = match28 - match32;
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diff16 = match16 - match32;
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if (diff32*2 > diff16)
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fskout = 2'b10;
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else if (!last0)
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begin
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fskout = 2'b10;
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end
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end
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end
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end
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end
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end
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end
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end
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`endif
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// A couple of registers in which to accumulate the correlations. From the 64 samples
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// we would add at most 32 times the difference between unmodulated and modulated signal. It should
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@ -89,7 +183,6 @@ reg signed [13:0] corr_q_accum;
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reg signed [7:0] corr_i_out;
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reg signed [7:0] corr_q_out;
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// the amplitude of the subcarrier is sqrt(ci^2 + cq^2).
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// approximate by amplitude = max(|ci|,|cq|) + 1/2*min(|ci|,|cq|)
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reg [13:0] corr_amplitude, abs_ci, abs_cq, max_ci_cq;
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@ -122,7 +215,6 @@ begin
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end
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// The subcarrier reference signals
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reg subcarrier_I;
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reg subcarrier_Q;
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@ -130,23 +222,22 @@ reg subcarrier_Q;
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always @(*)
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begin
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if (subcarrier_frequency == `FPGA_HF_READER_SUBCARRIER_848_KHZ)
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begin
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subcarrier_I = ~corr_i_cnt[3];
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subcarrier_Q = ~(corr_i_cnt[3] ^ corr_i_cnt[2]);
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end
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begin
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subcarrier_I = ~corr_i_cnt[3];
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subcarrier_Q = ~(corr_i_cnt[3] ^ corr_i_cnt[2]);
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end
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else if (subcarrier_frequency == `FPGA_HF_READER_SUBCARRIER_212_KHZ)
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begin
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subcarrier_I = ~corr_i_cnt[5];
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subcarrier_Q = ~(corr_i_cnt[5] ^ corr_i_cnt[4]);
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end
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begin
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subcarrier_I = ~corr_i_cnt[5];
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subcarrier_Q = ~(corr_i_cnt[5] ^ corr_i_cnt[4]);
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end
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else
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begin // 424 kHz
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subcarrier_I = ~corr_i_cnt[4];
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subcarrier_Q = ~(corr_i_cnt[4] ^ corr_i_cnt[3]);
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end
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begin // 424 kHz
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subcarrier_I = ~corr_i_cnt[4];
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subcarrier_Q = ~(corr_i_cnt[4] ^ corr_i_cnt[3]);
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end
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end
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// ADC data appears on the rising edge, so sample it on the falling edge
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always @(negedge adc_clk)
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begin
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@ -157,9 +248,20 @@ begin
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begin
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if (minor_mode == `FPGA_HF_READER_MODE_SNIFF_AMPLITUDE)
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begin
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// send amplitude plus 2 bits reader signal
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corr_i_out <= corr_amplitude[13:6];
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corr_q_out <= {corr_amplitude[5:0], after_hysteresis_prev_prev, after_hysteresis_prev};
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`ifdef WITH_HF_15
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if (subcarrier_frequency == `FPGA_HF_READER_2SUBCARRIERS_424_484_KHZ)
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begin
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// send amplitude + 2 bits fsk (2sc) signal + 2 bits reader signal
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corr_i_out <= corr_amplitude[13:6];
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corr_q_out <= {corr_amplitude[5:2], fskout, after_hysteresis_prev_prev, after_hysteresis_prev};
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end
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else
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`endif
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begin
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// send amplitude plus 2 bits reader signal
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corr_i_out <= corr_amplitude[13:6];
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corr_q_out <= {corr_amplitude[5:0], after_hysteresis_prev_prev, after_hysteresis_prev};
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end
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end
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else if (minor_mode == `FPGA_HF_READER_MODE_SNIFF_IQ)
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begin
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@ -183,13 +285,23 @@ begin
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end
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else if (minor_mode == `FPGA_HF_READER_MODE_RECEIVE_AMPLITUDE)
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begin
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// send amplitude
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corr_i_out <= {2'b00, corr_amplitude[13:8]};
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corr_q_out <= corr_amplitude[7:0];
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`ifdef WITH_HF_15
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if (subcarrier_frequency == `FPGA_HF_READER_2SUBCARRIERS_424_484_KHZ)
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begin
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// send 2 bits fsk (2sc) signal + amplitude
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corr_i_out <= {fskout, corr_amplitude[13:8]};
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corr_q_out <= corr_amplitude[7:0];
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end
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else
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`endif
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begin
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// send amplitude
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corr_i_out <= {2'b00, corr_amplitude[13:8]};
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corr_q_out <= corr_amplitude[7:0];
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end
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end
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else if (minor_mode == `FPGA_HF_READER_MODE_RECEIVE_IQ)
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begin
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// Send 8 bits of in phase tag signal
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if (corr_i_accum[13:11] == 3'b000 || corr_i_accum[13:11] == 3'b111)
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corr_i_out <= corr_i_accum[11:4];
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@ -251,7 +363,6 @@ begin
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end
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// ssp clock and frame signal for communication to and from ARM
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// _____ _____ _____ _
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// ssp_clk | |_____| |_____| |_____|
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@ -262,7 +373,6 @@ end
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//
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// corr_i_cnt 0 1 2 3 4 5 6 7 8 9 10 11 12 ...
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//
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always @(negedge adc_clk)
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begin
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if (corr_i_cnt[1:0] == 2'b00)
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@ -280,10 +390,8 @@ begin
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ssp_frame <= 1'b0;
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end
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assign ssp_din = corr_i_out[7];
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// a jamming signal
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reg jam_signal;
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reg [3:0] jam_counter;
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@ -333,7 +441,7 @@ assign pwr_oe1 = 1'b0;
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assign pwr_oe3 = 1'b0;
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// Unused.
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assign pwr_lo = 1'b0;
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assign pwr_lo = 1'b0;
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assign pwr_oe2 = 1'b0;
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// Debug Output
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