Revert "WIP: Clean Legic Reader"

fpga/hi_read_tx.v

@@ -71,8 +71,19 @@ always @(negedge ssp_clk)
 
 assign ssp_frame = (hi_byte_div == 3'b000);
 
-assign ssp_din = 1'b0;
+// Implement a hysteresis to give out the received signal on
+// ssp_din. Sample at fc.
+assign adc_clk = ck_1356meg;
 
-assign dbg = ssp_frame;
+// ADC data appears on the rising edge, so sample it on the falling edge
+reg after_hysteresis;
+always @(negedge adc_clk)
+begin
+    if(& adc_d[6:4]) after_hysteresis <= 1'b1;
+    else if(~(| adc_d[6:4])) after_hysteresis <= 1'b0;
+end
 
-endmodule
+assign ssp_din = after_hysteresis;
+assign dbg = after_hysteresis;
+
+endmodule