diff --git a/CHANGELOG.md b/CHANGELOG.md index 73db91565..5783b0f46 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -3,6 +3,8 @@ All notable changes to this project will be documented in this file. This project uses the changelog in accordance with [keepchangelog](http://keepachangelog.com/). Please use this to write notable changes, which is not the same as git commit log... ## [unreleased][unreleased] + - Rebuilt the Spartan-2 `fpga_*.bit` files to include the `hi_iso14443a.v` update (@d18c7db) + - Added minor orphaned change from `hi_iso14443a.v` in `fpga-xc3s100e` to `hi_iso14443a.v` in `fpga-xc2s30` (@d18c7db) - Added python3 script to convert amiibo nfc Flipper Zero files to eml files to be used with Proxmark3 (@OscarAkaElvis) - Changed `hf mf restore` - Auth both key A and key B with default password (@wh201906) - Changed `nfc decode -f` - now can detect and convert MFC dumpfiles to NDEF byte arrays (@iceman1001) diff --git a/fpga-xc2s30/fpga_felica.bit b/fpga-xc2s30/fpga_felica.bit index d87b879de..83009b499 100644 Binary files a/fpga-xc2s30/fpga_felica.bit and b/fpga-xc2s30/fpga_felica.bit differ diff --git a/fpga-xc2s30/fpga_hf.bit b/fpga-xc2s30/fpga_hf.bit index ce658c702..06a4569f9 100644 Binary files a/fpga-xc2s30/fpga_hf.bit and b/fpga-xc2s30/fpga_hf.bit differ diff --git a/fpga-xc2s30/fpga_hf_15.bit b/fpga-xc2s30/fpga_hf_15.bit index 30db5253b..0e59dd3d0 100644 Binary files a/fpga-xc2s30/fpga_hf_15.bit and b/fpga-xc2s30/fpga_hf_15.bit differ diff --git a/fpga-xc2s30/fpga_lf.bit b/fpga-xc2s30/fpga_lf.bit index d8ff55b32..93a26841a 100644 Binary files a/fpga-xc2s30/fpga_lf.bit and b/fpga-xc2s30/fpga_lf.bit differ diff --git a/fpga-xc2s30/hi_iso14443a.v b/fpga-xc2s30/hi_iso14443a.v index 81643b8c3..c9bc64f94 100644 --- a/fpga-xc2s30/hi_iso14443a.v +++ b/fpga-xc2s30/hi_iso14443a.v @@ -222,17 +222,29 @@ reg signed [10:0] rx_mod_falling_edge_max; reg signed [10:0] rx_mod_rising_edge_max; reg curbit; -`define EDGE_DETECT_THRESHOLD 5 +`define EDGE_DETECT_THRESHOLD 3 +`define EDGE_DETECT_THRESHOLDHIGH 20 always @(negedge adc_clk) begin if(negedge_cnt[3:0] == mod_detect_reset_time) begin - // detect modulation signal: if modulating, there must have been a falling AND a rising edge - if ((rx_mod_falling_edge_max > `EDGE_DETECT_THRESHOLD) && (rx_mod_rising_edge_max < -`EDGE_DETECT_THRESHOLD)) - curbit <= 1'b1; // modulation - else - curbit <= 1'b0; // no modulation + if (mod_type == `FPGA_HF_ISO14443A_SNIFFER) + begin + // detect modulation signal: if modulating, there must have been a falling AND a rising edge + if ((rx_mod_falling_edge_max > `EDGE_DETECT_THRESHOLDHIGH) && (rx_mod_rising_edge_max < -`EDGE_DETECT_THRESHOLDHIGH)) + curbit <= 1'b1; // modulation + else + curbit <= 1'b0; // no modulation + end + else + begin + // detect modulation signal: if modulating, there must have been a falling AND a rising edge + if ((rx_mod_falling_edge_max > `EDGE_DETECT_THRESHOLD) && (rx_mod_rising_edge_max < -`EDGE_DETECT_THRESHOLD)) + curbit <= 1'b1; // modulation + else + curbit <= 1'b0; // no modulation + end // reset modulation detector rx_mod_rising_edge_max <= 0; rx_mod_falling_edge_max <= 0;