mirror of
https://github.com/RfidResearchGroup/proxmark3.git
synced 2025-08-14 10:37:23 -07:00
Fix corrupted data caused by CMD_WTX
No need to wait for 2.5s (1s + FPGA_LOAD_WAIT_TIME) if the real-time sampling stops. Make sure the LF bitstream is loaded before real-time sampling so the response of CMD_WTX won't appear.
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6 changed files with 32 additions and 19 deletions
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@ -3,6 +3,7 @@ All notable changes to this project will be documented in this file.
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This project uses the changelog in accordance with [keepchangelog](http://keepachangelog.com/). Please use this to write notable changes, which is not the same as git commit log...
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## [unreleased][unreleased]
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- Fixed the corrupted data in real-time sampling (@wh201906)
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- Added a slider in the plot window for navigation (@wh201906)
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- Fixed client build bug with Python 3.12 (@wh201906)
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- Fixed `ExchangeAPDUSC()` in `cmdsmartcard.c` to prevent client crash (@wh201906)
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@ -24,12 +24,6 @@
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#define FpgaDisableSscDma(void) AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
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#define FpgaEnableSscDma(void) AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN;
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// definitions for multiple FPGA config files support
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#define FPGA_BITSTREAM_LF 1
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#define FPGA_BITSTREAM_HF 2
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#define FPGA_BITSTREAM_HF_FELICA 3
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#define FPGA_BITSTREAM_HF_15 4
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/*
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Communication between ARM / FPGA is done inside armsrc/fpgaloader.c see: function FpgaSendCommand()
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Send 16 bit command / data pair to FPGA with the bit format:
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@ -4249,7 +4249,7 @@ int CmdHF14AMfELoad(const char *Cmd) {
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// ICEMAN: bug. if device has been using ICLASS commands,
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// the device needs to load the HF fpga image. It takes 1.5 second.
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set_fpga_mode(2);
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set_fpga_mode(FPGA_BITSTREAM_HF);
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// use RDV4 spiffs
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if (use_spiffs && IfPm3Flash() == false) {
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@ -8006,7 +8006,7 @@ static int CmdHF14AGen4Save(const char *Cmd) {
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// ICEMAN: bug. if device has been using ICLASS commands,
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// the device needs to load the HF fpga image. It takes 1.5 second.
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set_fpga_mode(2);
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set_fpga_mode(FPGA_BITSTREAM_HF);
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// validations
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if (pwd_len != 4 && pwd_len != 0) {
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@ -1105,7 +1105,7 @@ static int CmdBreak(const char *Cmd) {
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}
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int set_fpga_mode(uint8_t mode) {
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if (mode < 1 || mode > 4) {
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if (mode < FPGA_BITSTREAM_LF || mode > FPGA_BITSTREAM_HF_15) {
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return PM3_EINVARG;
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}
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uint8_t d[] = {mode};
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@ -30,6 +30,7 @@
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#include "cliparser.h" // args parsing
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#include "graph.h" // for graph data
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#include "cmddata.h" // for `lf search`
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#include "cmdhw.h" // for setting FPGA image
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#include "cmdlfawid.h" // for awid menu
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#include "cmdlfem.h" // for em menu
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#include "cmdlfem410x.h" // for em4x menu
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@ -725,15 +726,23 @@ static int lf_read_internal(bool realtime, bool verbose, uint64_t samples) {
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size_t sample_bytes = samples * bits_per_sample;
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sample_bytes = (sample_bytes / 8) + (sample_bytes % 8 != 0);
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// In real-time mode, the LF bitstream should be loaded before receiving raw data.
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// Otherwise, the first batch of raw data might contain the response of CMD_WTX.
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int result = set_fpga_mode(FPGA_BITSTREAM_LF);
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if (result != PM3_SUCCESS) {
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PrintAndLogEx(FAILED, "failed to load LF bitstream to FPGA");
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return result;
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}
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SendCommandNG(CMD_LF_ACQ_RAW_ADC, (uint8_t *)&payload, sizeof(payload));
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if (is_trigger_threshold_set) {
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size_t first_receive_len = 32; // larger than the response of CMD_WTX
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size_t first_receive_len = 32;
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// Wait until a bunch of data arrives
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first_receive_len = WaitForRawDataTimeout(realtimeBuf, first_receive_len, -1, false);
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sample_bytes = WaitForRawDataTimeout(realtimeBuf + first_receive_len, sample_bytes - first_receive_len, 1000 + FPGA_LOAD_WAIT_TIME, true);
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sample_bytes = WaitForRawDataTimeout(realtimeBuf + first_receive_len, sample_bytes - first_receive_len, 1000, true);
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sample_bytes += first_receive_len;
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} else {
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sample_bytes = WaitForRawDataTimeout(realtimeBuf, sample_bytes, 1000 + FPGA_LOAD_WAIT_TIME, true);
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sample_bytes = WaitForRawDataTimeout(realtimeBuf, sample_bytes, 1000, true);
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}
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samples = sample_bytes * 8 / bits_per_sample;
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PrintAndLogEx(INFO, "Done: %" PRIu64 " samples (%zu bytes)", samples, sample_bytes);
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@ -767,8 +776,6 @@ int lf_read(bool verbose, uint64_t samples) {
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}
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int CmdLFRead(const char *Cmd) {
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// In real-time mode, the first few bytes might be the response of CMD_WTX
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// rather than the real samples if the LF FPGA image is not ready.
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CLIParserContext *ctx;
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CLIParserInit(&ctx, "lf read",
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"Sniff low frequency signal.\n"
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@ -837,15 +844,23 @@ int lf_sniff(bool realtime, bool verbose, uint64_t samples) {
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size_t sample_bytes = samples * bits_per_sample;
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sample_bytes = (sample_bytes / 8) + (sample_bytes % 8 != 0);
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// In real-time mode, the LF bitstream should be loaded before receiving raw data.
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// Otherwise, the first batch of raw data might contain the response of CMD_WTX.
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int result = set_fpga_mode(FPGA_BITSTREAM_LF);
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if (result != PM3_SUCCESS) {
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PrintAndLogEx(FAILED, "failed to load LF bitstream to FPGA");
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return result;
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}
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SendCommandNG(CMD_LF_SNIFF_RAW_ADC, (uint8_t *)&payload, sizeof(payload));
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if (is_trigger_threshold_set) {
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size_t first_receive_len = 32; // larger than the response of CMD_WTX
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size_t first_receive_len = 32;
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// Wait until a bunch of data arrives
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first_receive_len = WaitForRawDataTimeout(realtimeBuf, first_receive_len, -1, false);
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sample_bytes = WaitForRawDataTimeout(realtimeBuf + first_receive_len, sample_bytes - first_receive_len, 1000 + FPGA_LOAD_WAIT_TIME, true);
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sample_bytes = WaitForRawDataTimeout(realtimeBuf + first_receive_len, sample_bytes - first_receive_len, 1000, true);
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sample_bytes += first_receive_len;
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} else {
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sample_bytes = WaitForRawDataTimeout(realtimeBuf, sample_bytes, 1000 + FPGA_LOAD_WAIT_TIME, true);
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sample_bytes = WaitForRawDataTimeout(realtimeBuf, sample_bytes, 1000, true);
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}
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samples = sample_bytes * 8 / bits_per_sample;
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PrintAndLogEx(INFO, "Done: %" PRIu64 " samples (%zu bytes)", samples, sample_bytes);
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@ -875,8 +890,6 @@ int lf_sniff(bool realtime, bool verbose, uint64_t samples) {
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}
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int CmdLFSniff(const char *Cmd) {
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// In real-time mode, the first few bytes might be the response of CMD_WTX
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// rather than the real samples if the LF FPGA image is not ready.
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CLIParserContext *ctx;
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CLIParserInit(&ctx, "lf sniff",
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"Sniff low frequency signal. You need to configure the LF part on the Proxmark3 device manually.\n"
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@ -847,6 +847,11 @@ typedef struct {
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# define UART_TCP_LOCAL_CLIENT_RX_TIMEOUT_MS 40
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# define UART_UDP_LOCAL_CLIENT_RX_TIMEOUT_MS 20
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// definitions for multiple FPGA config files support
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#define FPGA_BITSTREAM_LF 1
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#define FPGA_BITSTREAM_HF 2
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#define FPGA_BITSTREAM_HF_FELICA 3
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#define FPGA_BITSTREAM_HF_15 4
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// CMD_DEVICE_INFO response packet has flags in arg[0], flag definitions:
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/* Whether a bootloader that understands the g_common_area is present */
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