mirror of
https://github.com/RfidResearchGroup/proxmark3.git
synced 2025-08-14 10:37:23 -07:00
div errors
This commit is contained in:
tharexde
parent
48495bf272
commit
b96b92249f
1 changed files with 3 additions and 327 deletions
330
armsrc/em4x50.c
330
armsrc/em4x50.c
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@ -236,62 +236,6 @@ static void em4x50_setup_read(void) {
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WDT_HIT();
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}
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static void em4x50_setup_sim(void) {
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StopTicks();
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FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
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sample_config *sc = getSamplingConfig();
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sc->decimation = 1;
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sc->averaging = 0;
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//FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc->divisor);
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, LF_DIVISOR_125);
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// FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC);
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// Connect the A/D to the peak-detected low-frequency path.
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SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
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// Now set up the SSC to get the ADC samples that are now streaming at us.
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FpgaSetupSsc();
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// Steal this pin from the SSP (SPI communication channel with fpga) and use it to control the modulation
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AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
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AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
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LOW(GPIO_SSC_DOUT);
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// Enable peripheral Clock for TIMER_CLOCK 0
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AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0);
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AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
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//AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV4_CLOCK;
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AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK;
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// Enable peripheral Clock for TIMER_CLOCK 1
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AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
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AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
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//AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV4_CLOCK;
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AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK;
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// Clear all leds
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LEDsoff();
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// Reset and enable timers
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AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
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AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
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// Prepare data trace
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uint32_t bufsize = 10000;
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// use malloc
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if (g_logging) initSampleBufferEx(&bufsize, true);
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lf_sample_mean();
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}
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// functions for "reader" use case
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static bool get_signalproperties(void) {
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@ -301,6 +245,7 @@ static bool get_signalproperties(void) {
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bool signal_found = false;
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int no_periods = 32, pct = 75, noise = 140;
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uint8_t sample = 0;
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uint8_t sample_ref = 127;
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uint8_t sample_max_mean = 0;
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uint8_t sample_max[no_periods];
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@ -377,8 +322,6 @@ static int get_next_bit(void) {
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static uint32_t get_pulse_length(void) {
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int32_t timeout = (T0 * 3 * EM4X50_T_TAG_FULL_PERIOD);
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// iterates pulse length (low -> high -> low)
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// to avoid endless loops - quit after EM4X50_SAMPLE_CNT_MAX samples
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@ -394,8 +337,6 @@ static uint32_t get_pulse_length(void) {
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}
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AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG;
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timeout = (T0 * 3 * EM4X50_T_TAG_FULL_PERIOD);
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sample_cnt = 0;
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while (sample < gHigh) {
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@ -811,7 +752,7 @@ static bool check_ack(bool bliw) {
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return false;
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}
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static int get_word_from_bitstream(uintö8_t bits[EM4X50_TAG_WORD]) {
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static int get_word_from_bitstream(uint8_t bits[EM4X50_TAG_WORD]) {
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// decodes one word by evaluating pulse lengths and previous bit;
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// word must have 45 bits in total:
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@ -937,13 +878,8 @@ static bool reset(void) {
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if (request_receive_mode()) {
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// send login command
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<<<<<<< Updated upstream
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em4x50_send_byte_with_parity(EM4X50_COMMAND_RESET);
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=======
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em4x50_reader_send_byte_with_parity(EM4X50_COMMAND_RESET);
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>>>>>>> Stashed changes
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if (check_ack(false))
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return true;
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@ -1391,32 +1327,6 @@ static bool em4x50_sim_send_byte_with_parity2(uint8_t byte) {
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return true;
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}
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static bool em4x50_sim_send_word2(uint8_t *word) {
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uint8_t cparity = 0x00;
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// 4 bytes each with even row parity bit
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for (int i = 0; i < 4; i++)
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if (!em4x50_sim_send_byte_with_parity2(word[i]))
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return false;
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// column parity
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for (int i = 0; i < 8; i++) {
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cparity <<= 1;
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for (int j = 0; j < 4; j++) {
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cparity ^= (word[j] >> i) & 1;
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}
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}
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if (!em4x50_sim_send_byte2(cparity))
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return false;
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// stop bit
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if (!em4x50_sim_send_bit2(0))
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return false;
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return true;
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}
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bool em4x50_sim_send_word3(uint32_t word) {
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uint8_t cparity = 0x00;
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@ -1491,81 +1401,6 @@ bool em4x50_sim_send_listen_window2(void) {
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return true;
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}
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static bool em4x50_sim_send_listen_window3(void) {
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int t = 0;
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int i = 0;
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uint16_t check = 0;
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uint8_t test[100] = {0};
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while (t < 5 * EM4X50_T_TAG_FULL_PERIOD) {
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// wait until SSC_CLK goes HIGH
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while (!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
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WDT_HIT();
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if (check == 1000) {
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if (BUTTON_PRESS())
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return false;
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check = 0;
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}
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++check;
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}
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if (t >= 4 * EM4X50_T_TAG_FULL_PERIOD) {
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SHORT_COIL();
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} else if (t >= 3 * EM4X50_T_TAG_FULL_PERIOD) {
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OPEN_COIL();
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i = 0;
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC);
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AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
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while (AT91C_BASE_TC0->TC_CV < T0 * EM4X50_T_TAG_FULL_PERIOD) {
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if (i == 0) {
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC);
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FpgaSetupSsc();
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//SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
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}
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if (i < 100)
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test[i++] = AT91C_BASE_SSC->SSC_RHR;
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}
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
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t = 4 * EM4X50_T_TAG_FULL_PERIOD - 1;
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} else if (t >= EM4X50_T_TAG_FULL_PERIOD) {
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SHORT_COIL();
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} else if (t >= EM4X50_T_TAG_HALF_PERIOD) {
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OPEN_COIL();
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} else {
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SHORT_COIL();
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}
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t++;
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check = 0;
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//wait until SSC_CLK goes LOW
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while (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
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WDT_HIT();
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if (check == 1000) {
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if (BUTTON_PRESS())
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return false;
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check = 0;
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}
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++check;
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}
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}
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for (i = 0; i < 100; i++)
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Dbprintf("value[%i] = %i", i, test[i]);
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return true;
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}
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/*
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static void em4x50_sim_send_word3(uint8_t *word) {
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@ -1660,112 +1495,6 @@ static void simlf(uint8_t *buf, int period) {
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void em4x50_sim(em4x50_data_t *etd) {
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bool bsuccess = false;
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//init_tag();
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//em4x50_setup_sim();
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//FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
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//StartTicks();
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//FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_MAJOR_MODE_LF_ADC );
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//FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_TOGGLE_MODE );
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//FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC);
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//FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
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//WaitMS(20);
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//FpgaSendCommand(FPGA_CMD_SET_DIVISOR, LF_DIVISOR_125);
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//AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
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//AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
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//AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
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// from hitag2
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//SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
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//FpgaSetupSsc();
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//AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
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//AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
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//LOW(GPIO_SSC_DOUT);
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//AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK;
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FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
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// works!
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//FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
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//FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_TOGGLE_MODE );
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// does not really work
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//FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC);
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//FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_MAJOR_MODE_LF_ADC );
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//FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
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//FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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// does not work!
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//FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
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//FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_ADC_READER_FIELD);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, LF_DIVISOR_125);
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//AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
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AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
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//AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
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AT91C_BASE_PMC->PMC_PCER |= (1 << AT91C_ID_TC0);
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AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;
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AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
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AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK;
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AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
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while (AT91C_BASE_TC0->TC_CV > 0) {}; // wait until TC1 returned to zero
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uint8_t word1[4] = {0x27, 0xfc, 0x42, 0x40};
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uint8_t word2[4] = {0x12, 0x34, 0x56, 0x78};
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bsuccess = em4x50_sim_send_listen_window3();
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while (bsuccess) {
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bsuccess = em4x50_sim_send_listen_window3()
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& em4x50_sim_send_word2(word1)
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& em4x50_sim_send_listen_window3()
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& em4x50_sim_send_word2(word2)
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& em4x50_sim_send_listen_window3();
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}
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/*
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WDT_HIT();
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while (BUTTON_PRESS() == false) {
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if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
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for (int i = 0; i < 10; i++) {
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HIGH(GPIO_SSC_DOUT);
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lf_wait_periods(32);
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Dbprintf("High");
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LOW(GPIO_SSC_DOUT);
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lf_wait_periods(32);
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Dbprintf("Low");
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}
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Dbprintf("geht");
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} else {
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Dbprintf("Mist");
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}
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}
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*/
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/*
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volatile uint8_t adc_val[2000] = {0};
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//FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC);
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//SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
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//FpgaSetupSsc();
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while (BUTTON_PRESS() == false) {
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if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY))
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for (int i = 0; i < 2000; i++)
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adc_val[i] = AT91C_BASE_SSC->SSC_RHR;
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}
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for (int i = 0; i < 2000; i++)
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Dbprintf("adc_val = %i", adc_val[i]);
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*/
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lf_finalize();
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reply_ng(CMD_ACK, bsuccess, (uint8_t *)tag.sectors, 238);
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@ -1773,60 +1502,7 @@ void em4x50_sim(em4x50_data_t *etd) {
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void em4x50_test(em4x50_data_t *etd) {
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DBGLEVEL = DBG_DEBUG;
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bool bsuccess = false;
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em4x50_setup_sim();
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//FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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//FpgaSetupSsc();
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//AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;
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if (etd->carrier == 1) {
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LED_A_ON();
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LOW(GPIO_SSC_DOUT);
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if (DBGLEVEL >= DBG_DEBUG)
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Dbprintf("carrier on");
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} else if (etd->carrier == 0) {
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LED_A_OFF();
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HIGH(GPIO_SSC_DOUT);
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if (DBGLEVEL >= DBG_DEBUG)
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Dbprintf("carrier off");
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} else {
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LED_B_ON();
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LOW(GPIO_SSC_DOUT);
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while (BUTTON_PRESS() == false) {
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for (int i = 0; i < 10; i++)
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wait_timer(0, T0 * EM4X50_T_TAG_FULL_PERIOD);
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LED_C_ON();
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// send selective read command
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em4x50_reader_send_byte_with_parity(EM4X50_COMMAND_SELECTIVE_READ);
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em4x50_reader_send_bit(0);
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em4x50_reader_send_bit(0);
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em4x50_reader_send_byte_with_parity(etd->byte);
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LED_C_OFF();
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}
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LED_B_OFF();
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lf_finalize();
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}
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bsuccess = true;
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bool bsuccess = true;
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reply_ng(CMD_ACK, bsuccess, (uint8_t *)tag.sectors, 238);
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}
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