mirror of
https://github.com/RfidResearchGroup/proxmark3.git
synced 2025-08-14 02:27:26 -07:00
CHG: a better micro second (us) spindely function. At average it has 8-10us delay, but its linear. Making error less when you want to wait longer..
SpinDelayCountUs(20) gives a delay of 28us. SpinDelayCountUs(100) gives a delay of 110us. SpinDelayCountUs(500) gives a delay of 508us.
This commit is contained in:
iceman1001
parent
f72669f366
commit
b4a6775b5e
4 changed files with 116 additions and 107 deletions
162
armsrc/legicrf.c
162
armsrc/legicrf.c
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@ -63,17 +63,15 @@ static void setup_timer(void) {
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//#define RWD_TIME_0 90 /* RWD_TIME_PAUSE off, 40us on = 60us */
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//#define RWD_TIME_PAUSE 30 /* 20us */
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#define RWD_TIME_1 80 /* READER_TIME_PAUSE off, 80us on = 100us */
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#define RWD_TIME_0 40 /* READER_TIME_PAUSE off, 40us on = 60us */
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#define RWD_TIME_PAUSE 20 /* 20us */
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#define RWD_TIME_1 80-4 /* READER_TIME_PAUSE off, 80us on = 100us */
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#define RWD_TIME_0 40-4 /* READER_TIME_PAUSE off, 40us on = 60us */
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#define RWD_TIME_PAUSE 20-4 /* 20us */
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#define TAG_BIT_PERIOD 100 // 100us for every bit
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#define TAG_BIT_PERIOD 100-8 // 100us for every bit
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#define RWD_TIME_FUZZ 20 /* rather generous 13us, since the peak detector + hysteresis fuzz quite a bit */
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//#define TAG_TIME_WAIT 490 /* 490 time from READER frame end to TAG frame start, experimentally determined */
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#define TAG_TIME_WAIT 258 // 330us from READER frame end to TAG frame start, experimentally determined
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#define TAG_TIME_WAIT 330 // 330us from READER frame end to TAG frame start, experimentally determined (490)
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#define RDW_TIME_WAIT 258 //
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@ -86,24 +84,19 @@ static void setup_timer(void) {
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#ifndef SHORT_COIL
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//#define LOW(x) AT91C_BASE_PIOA->PIO_CODR = (x)
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# define SHORT_COIL() LOW(GPIO_SSC_DOUT);
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# define SHORT_COIL LOW(GPIO_SSC_DOUT);
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#endif
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#ifndef OPEN_COIL
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//#define HIGH(x) AT91C_BASE_PIOA->PIO_SODR = (x)
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# define OPEN_COIL() HIGH(GPIO_SSC_DOUT);
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# define OPEN_COIL HIGH(GPIO_SSC_DOUT);
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#endif
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uint32_t stop_send_frame_us = 0;
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// ~ 258us + 100us*delay
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#define WAIT(delay) SpinDelayUs(delay);
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#define WAIT_100 WAIT(100)
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#define COIL_PULSE(delay) \
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SHORT_COIL() \
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SpinDelayUs(RWD_TIME_PAUSE); \
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OPEN_COIL() \
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SpinDelayUs(delay);
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#define WAIT(delay) SpinDelayCountUs((delay));
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#define COIL_PULSE(x) { SHORT_COIL; WAIT(RWD_TIME_PAUSE); OPEN_COIL; WAIT((x)); }
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#define COIL_PULSE_PAUSE { SHORT_COIL; WAIT(RWD_TIME_PAUSE); OPEN_COIL; }
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// ToDo: define a meaningful maximum size for auth_table. The bigger this is, the lower will be the available memory for traces.
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// Historically it used to be FREE_BUFFER_SIZE, which was 2744.
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@ -121,9 +114,22 @@ static void ResetClock(void){
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Reset(timer);
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}
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static void frame_append_bit(struct legic_frame * const f, int bit) {
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// Overflow, won't happen
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if (f->bits >= 31) return;
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f->data |= (bit << f->bits);
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f->bits++;
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}
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static void frame_clean(struct legic_frame * const f) {
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f->data = 0;
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f->bits = 0;
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}
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// Prng works when waiting in 99.1us cycles.
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// and while sending/receiving in bit frames (100, 60)
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static void CalibratePrng( uint32_t time){
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/*static void CalibratePrng( uint32_t time){
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// Calculate Cycles based on timer 100us
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uint32_t i = (time - stop_send_frame_us) / 100 ;
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@ -134,6 +140,7 @@ static void CalibratePrng( uint32_t time){
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if ( k > 0 )
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legic_prng_forward(k);
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}
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*/
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/* Generate Keystream */
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static uint32_t get_key_stream(int skip, int count)
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@ -205,7 +212,7 @@ static void frame_send_tag(uint16_t response, uint8_t bits, uint8_t crypt) {
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else
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LOW(GPIO_SSC_DOUT);
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WAIT_100
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WAIT(100)
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}
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LOW(GPIO_SSC_DOUT);
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}
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@ -226,20 +233,20 @@ static void frame_sendAsReader(uint32_t data, uint8_t bits){
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for (; mask < BITMASK(bits); mask <<= 1) {
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if (send & mask) {
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COIL_PULSE(RWD_TIME_1)
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COIL_PULSE(RWD_TIME_1);
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} else {
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COIL_PULSE(RWD_TIME_0)
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COIL_PULSE(RWD_TIME_0);
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}
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}
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// One final pause to mark the end of the frame
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COIL_PULSE(0)
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// log
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COIL_PULSE_PAUSE;
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stop_send_frame_us = GetCountUS();
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uint8_t cmdbytes[] = {
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data & 0xFF,
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(data >> 8) & 0xFF,
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bits,
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lfsr & 0xFF,
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(lfsr >> 8) & 0xFF,
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prng1,
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@ -271,62 +278,60 @@ static void frame_sendAsReader(uint32_t data, uint8_t bits){
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*/
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static void frame_receiveAsReader(struct legic_frame * const f, uint8_t bits, uint8_t crypt) {
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uint32_t starttime = GetCountUS();
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frame_clean(f);
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uint8_t i = 0;
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uint32_t the_bit = 1;
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uint32_t next_bit_at;
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uint32_t data;/* Use a bitmask to save on shifts */
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int old_level = 0, edges = 0, level = 0;
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uint8_t i = 0, edges = 0;
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uint16_t lsfr = 0;
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uint32_t the_bit = 1, next_bit_at, data;
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int old_level = 0, level = 0;
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if(bits > 32) bits = 32;
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AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
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AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
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uint32_t starttime = GetCountUS();
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// calibrate the prng.
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// the time between end-of-send and here, div 100us
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CalibratePrng( starttime );
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// calibrate the prng.
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legic_prng_forward(2);
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//CalibratePrng( starttime );
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// precompute the cipher
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uint8_t prng1 = legic_prng_count() ;
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uint8_t prng_before = legic_prng_count() ;
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if(crypt)
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data = legic_prng_get_bits(bits);
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lsfr = legic_prng_get_bits(bits);
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uint16_t lsfr = data;
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data = lsfr;
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next_bit_at = GetCountUS() + TAG_BIT_PERIOD;
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//FIXED time between sending frame and now listening frame. 330us
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uint32_t icetime = TAG_TIME_WAIT - ( GetCountUS() - stop_send_frame_us );
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//
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WAIT( icetime ); // 21.3us inc.
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AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
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AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
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// FIXED time between sending frame and now listening frame.
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WAIT(TAG_TIME_WAIT)
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//uint32_t iced = GetCountUS() - starttime;
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//uint32_t icetime = TAG_TIME_WAIT - iced;
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// if (icetime > TAG_TIME_WAIT)
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// icetime = TAG_TIME_WAIT;
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//WAIT( icetime )
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next_bit_at = GetCountUS();
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next_bit_at += TAG_BIT_PERIOD;
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for( i = 0; i < bits; i++) {
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edges = 0;
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while ( GetCountUS() < next_bit_at) {
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level = AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN;
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level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
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if (level != old_level)
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edges++;
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++edges;
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old_level = level;
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}
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next_bit_at += TAG_BIT_PERIOD;
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// We expect 42 edges == ONE
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if(edges > 20 && edges < 60) {
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DbpString("one");
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if(edges > 20 && edges < 60)
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data ^= the_bit;
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}
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the_bit <<= 1;
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}
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// output
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f->data = data;
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f->bits = bits;
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@ -334,25 +339,16 @@ static void frame_receiveAsReader(struct legic_frame * const f, uint8_t bits, ui
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uint8_t cmdbytes[] = {
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(data & 0xFF),
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(data >> 8) & 0xFF,
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bits,
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(lsfr & 0xFF),
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(lsfr >> 8) & 0xFF,
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prng1,
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legic_prng_count()
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prng_before,
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legic_prng_count(),
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icetime & 0xff,
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(icetime >> 8) & 0xFF
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};
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LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GetCountUS(), NULL, FALSE);
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}
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static void frame_append_bit(struct legic_frame * const f, int bit) {
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// Overflow, won't happen
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if (f->bits >= 31) return;
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f->data |= (bit << f->bits);
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f->bits++;
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}
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static void frame_clean(struct legic_frame * const f) {
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f->data = 0;
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f->bits = 0;
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}
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// Setup pm3 as a Legic Reader
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@ -360,7 +356,7 @@ static uint32_t perform_setup_phase_rwd(uint8_t iv) {
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// Switch on carrier and let the tag charge for 1ms
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HIGH(GPIO_SSC_DOUT);
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SpinDelay(40);
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SpinDelay(20);
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ResetUSClock();
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@ -373,8 +369,6 @@ static uint32_t perform_setup_phase_rwd(uint8_t iv) {
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// Now both tag and reader has same IV. Prng can start.
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legic_prng_init(iv);
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frame_clean(¤t_frame);
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frame_receiveAsReader(¤t_frame, 6, 1);
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// fixed delay before sending ack.
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@ -401,9 +395,9 @@ static uint32_t perform_setup_phase_rwd(uint8_t iv) {
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static void LegicCommonInit(void) {
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FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX);
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SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
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FpgaSetupSsc();
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX);
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/* Bitbang the transmitter */
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LOW(GPIO_SSC_DOUT);
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@ -427,11 +421,12 @@ static void switch_off_tag_rwd(void) {
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LOW(GPIO_SSC_DOUT);
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SpinDelay(10);
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WDT_HIT();
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set_tracing(FALSE);
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}
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// calculate crc4 for a legic READ command
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// 5,8,10 address size.
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static int LegicCRC(uint16_t byte_index, uint8_t value, uint8_t cmd_sz) {
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static uint32_t LegicCRC(uint16_t byte_index, uint8_t value, uint8_t cmd_sz) {
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crc_clear(&legic_crc);
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uint32_t temp = (value << cmd_sz) | (byte_index << 1) | LEGIC_READ;
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crc_update(&legic_crc, temp, cmd_sz + 8 );
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@ -443,20 +438,19 @@ static int LegicCRC(uint16_t byte_index, uint8_t value, uint8_t cmd_sz) {
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int legic_read_byte(int byte_index, int cmd_sz) {
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int calcCrc = 0;
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uint8_t byte = 0, crc = 0;
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uint32_t calcCrc = 0;
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uint32_t cmd = (byte_index << 1) | LEGIC_READ;
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legic_prng_forward(3);
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WAIT(300)
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WAIT(TAG_TIME_WAIT)
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frame_sendAsReader(cmd, cmd_sz);
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frame_clean(¤t_frame);
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frame_receiveAsReader(¤t_frame, 12, 1);
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byte = current_frame.data & 0xff;
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byte = current_frame.data & 0xFF;
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calcCrc = LegicCRC(byte_index, byte, cmd_sz);
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crc = (current_frame.data >> 8);
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@ -537,7 +531,12 @@ int LegicRfReader(int offset, int bytes, int iv) {
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int byte_index = 0, cmd_sz = 0, card_sz = 0;
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if ( MF_DBGLEVEL >= 2) Dbprintf("setting up legic card, IV = %x", iv);
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if ( MF_DBGLEVEL >= 2) {
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Dbprintf("setting up legic card, IV = %x", iv);
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Dbprintf("ONE %d ZERO %d PAUSE %d", RWD_TIME_1 , RWD_TIME_0 , RWD_TIME_PAUSE);
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Dbprintf("TAG BIT PERIOD %d FUZZ %d TAG WAIT TIME %d", TAG_BIT_PERIOD, RWD_TIME_FUZZ, TAG_TIME_WAIT);
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}
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LegicCommonInit();
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@ -1682,7 +1681,6 @@ int ice_legic_select_card()
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GetSamplesForLegicDemod(1000, TRUE);
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// frame_clean(¤t_frame);
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//frame_receiveAsReader(¤t_frame, 6, 1);
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legic_prng_forward(1); /* we wait anyways */
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@ -66,13 +66,13 @@ void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t periods, uint3
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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LED_D_ON();
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if(*(command++) == '0')
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SpinDelayUs(period_0);
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SpinDelayUs(period_0); // ICEMAN: problem with (us) clock is 21.3us increments
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else
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SpinDelayUs(period_1);
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SpinDelayUs(period_1); // ICEMAN: problem with (us) clock is 21.3us increments
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}
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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LED_D_OFF();
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SpinDelayUs(delay_off);
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SpinDelayUs(delay_off); // ICEMAN: problem with (us) clock is 21.3us increments
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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@ -228,17 +228,17 @@ void WriteTIbyte(uint8_t b)
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if (b&(1<<i)) {
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// stop modulating antenna
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LOW(GPIO_SSC_DOUT);
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SpinDelayUs(1000);
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SpinDelayUs(1000); // ICEMAN: problem with (us) clock is 21.3us increments
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// modulate antenna
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HIGH(GPIO_SSC_DOUT);
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SpinDelayUs(1000);
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SpinDelayUs(1000); // ICEMAN: problem with (us) clock is 21.3us increments
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} else {
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// stop modulating antenna
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LOW(GPIO_SSC_DOUT);
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SpinDelayUs(300);
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SpinDelayUs(300); // ICEMAN: problem with (us) clock is 21.3us increments
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// modulate antenna
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HIGH(GPIO_SSC_DOUT);
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SpinDelayUs(1700);
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SpinDelayUs(1700); // ICEMAN: problem with (us) clock is 21.3us increments
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}
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}
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}
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@ -437,7 +437,7 @@ void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
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if (gap) {
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WDT_HIT();
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SHORT_COIL();
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SpinDelayUs(gap);
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SpinDelayUs(gap); // ICEMAN: problem with (us) clock is 21.3us increments
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}
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}
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}
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@ -1116,7 +1116,7 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
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* Q5 tags seems to have issues when these values changes.
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*/
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#define START_GAP 31*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (or 15fc)
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#define START_GAP 50*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (or 15fc)
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#define WRITE_GAP 20*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (or 10fc)
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#define WRITE_0 18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (or 24fc)
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#define WRITE_1 50*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (or 56fc) 432 for T55x7; 448 for E5550
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@ -1144,7 +1144,7 @@ void TurnReadLFOn(int delay) {
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//int adcval = ((MAX_ADC_LF_VOLTAGE * AvgAdc(ADC_CHAN_LF)) >> 10);
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// where to save it
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SpinDelayUs(delay);
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SpinDelayUs(delay); // ICEMAN: problem with (us) clock is 21.3us increments
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}
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// Write one bit to card
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@ -1154,7 +1154,7 @@ void T55xxWriteBit(int bit) {
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else
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TurnReadLFOn(WRITE_1);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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SpinDelayUs(WRITE_GAP);
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SpinDelayUs(WRITE_GAP); // ICEMAN: problem with (us) clock is 21.3us increments
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}
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// Send T5577 reset command then read stream (see if we can identify the start of the stream)
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@ -1168,7 +1168,7 @@ void T55xxResetRead(void) {
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// Trigger T55x7 in mode.
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
|
||||
SpinDelayUs(START_GAP);
|
||||
SpinDelayUs(START_GAP); // ICEMAN: problem with (us) clock is 21.3us increments
|
||||
|
||||
// reset tag - op code 00
|
||||
T55xxWriteBit(0);
|
||||
|
|
@ -1198,7 +1198,7 @@ void T55xxWriteBlockExt(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg)
|
|||
|
||||
// Trigger T55x7 in mode.
|
||||
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
|
||||
SpinDelayUs(START_GAP);
|
||||
SpinDelayUs(START_GAP); // ICEMAN: problem with (us) clock is 21.3us increments
|
||||
|
||||
// Opcode 10
|
||||
T55xxWriteBit(1);
|
||||
|
|
@ -1247,17 +1247,18 @@ void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
|
|||
bool RegReadMode = (Block == 0xFF);
|
||||
|
||||
//clear buffer now so it does not interfere with timing later
|
||||
BigBuf_Clear_ext(false);
|
||||
BigBuf_Clear_keep_EM();
|
||||
|
||||
//make sure block is at max 7
|
||||
Block &= 0x7;
|
||||
|
||||
// Set up FPGA, 125kHz to power up the tag
|
||||
LFSetupFPGAForADC(95, true);
|
||||
SpinDelay(3);
|
||||
|
||||
// Trigger T55x7 Direct Access Mode with start gap
|
||||
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
|
||||
SpinDelayUs(START_GAP);
|
||||
SpinDelayUs(START_GAP); // ICEMAN: problem with (us) clock is 21.3us increments
|
||||
|
||||
// Opcode 1[page]
|
||||
T55xxWriteBit(1);
|
||||
|
|
@ -1273,8 +1274,8 @@ void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
|
|||
|
||||
// Send Block number (if direct access mode)
|
||||
if (!RegReadMode)
|
||||
for (i = 0x04; i != 0; i >>= 1)
|
||||
T55xxWriteBit(Block & i);
|
||||
for (i = 0x04; i != 0; i >>= 1)
|
||||
T55xxWriteBit(Block & i);
|
||||
|
||||
// Turn field on to read the response
|
||||
TurnReadLFOn(READ_GAP);
|
||||
|
|
@ -1297,7 +1298,7 @@ void T55xxWakeUp(uint32_t Pwd){
|
|||
|
||||
// Trigger T55x7 Direct Access Mode
|
||||
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
|
||||
SpinDelayUs(START_GAP);
|
||||
SpinDelayUs(START_GAP); // ICEMAN: problem with (us) clock is 21.3us increments
|
||||
|
||||
// Opcode 10
|
||||
T55xxWriteBit(1);
|
||||
|
|
@ -1628,20 +1629,20 @@ void SendForward(uint8_t fwd_bit_count) {
|
|||
fwd_bit_sz--; //prepare next bit modulation
|
||||
fwd_write_ptr++;
|
||||
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
|
||||
SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
|
||||
SpinDelayUs(55*8); //55 cycles off (8us each)for 4305 // ICEMAN: problem with (us) clock is 21.3us increments
|
||||
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
|
||||
SpinDelayUs(16*8); //16 cycles on (8us each)
|
||||
SpinDelayUs(16*8); //16 cycles on (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
|
||||
|
||||
// now start writting
|
||||
while(fwd_bit_sz-- > 0) { //prepare next bit modulation
|
||||
if(((*fwd_write_ptr++) & 1) == 1)
|
||||
SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
|
||||
SpinDelayUs(32*8); //32 cycles at 125Khz (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
|
||||
else {
|
||||
//These timings work for 4469/4269/4305 (with the 55*8 above)
|
||||
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
|
||||
SpinDelayUs(23*8); //16-4 cycles off (8us each)
|
||||
SpinDelayUs(23*8); //16-4 cycles off (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
|
||||
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
|
||||
SpinDelayUs(9*8); //16 cycles on (8us each)
|
||||
SpinDelayUs(9*8); //16 cycles on (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -236,10 +236,11 @@ int BUTTON_HELD(int ms) {
|
|||
// attempt at high resolution microsecond timer
|
||||
// beware: timer counts in 21.3uS increments (1024/48Mhz)
|
||||
void SpinDelayUs(int us) {
|
||||
int ticks = (48*us) >> 10;
|
||||
int ticks = (48 * us) >> 10;
|
||||
|
||||
// Borrow a PWM unit for my real-time clock
|
||||
AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
|
||||
|
||||
// 48 MHz / 1024 gives 46.875 kHz
|
||||
AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
|
||||
AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
|
||||
|
|
@ -352,7 +353,6 @@ uint32_t RAMFUNC GetCountUS(){
|
|||
// By suggestion from PwPiwi, http://www.proxmark.org/forum/viewtopic.php?pid=17548#p17548
|
||||
//return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV * 2) / 3);
|
||||
return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV << 1) / 3);
|
||||
//return (AT91C_BASE_TC1->TC_CV << 16) | ((AT91C_BASE_TC0->TC_CV << 1) / 3);
|
||||
}
|
||||
void ResetUSClock(void) {
|
||||
//enable clock of timer and software trigger
|
||||
|
|
@ -360,7 +360,16 @@ void ResetUSClock(void) {
|
|||
AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
|
||||
while (AT91C_BASE_TC1->TC_CV >= 1);
|
||||
}
|
||||
// attempt at high resolution microsecond timer
|
||||
// beware: timer counts in 21.3uS increments (1024/48Mhz)
|
||||
void SpinDelayCountUs(uint32_t us) {
|
||||
|
||||
us += GetCountUS();
|
||||
us -= 6;
|
||||
|
||||
for(;;)
|
||||
if ( GetCountUS() >= us ) return;
|
||||
}
|
||||
// static uint32_t GlobalUsCounter = 0;
|
||||
|
||||
// uint32_t RAMFUNC GetDeltaCountUS(){
|
||||
|
|
|
|||
|
|
@ -65,6 +65,7 @@ uint32_t RAMFUNC GetTickCount();
|
|||
void StartCountUS();
|
||||
uint32_t RAMFUNC GetCountUS();
|
||||
void ResetUSClock(void);
|
||||
void SpinDelayCountUs(uint32_t us);
|
||||
//uint32_t RAMFUNC GetDeltaCountUS();
|
||||
|
||||
void StartCountSspClk();
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue